Clik here to view.
ECO with Stratus HLS and the Digital Implementation Flow
For years chip designers have dealt with ECO’s when their source code was written in RTL. But the move to high-level synthesis (HLS) means that their source code is now one step further removed from...
View ArticleClik here to view.
2018 Annual HLS Survey Results
Earlier this year, we performed the annual high-level synthesis (HLS) industry survey to get an idea of the industry’s expectations of HLS. As in last year’s survey, approximately half of the responses...
View ArticleClik here to view.
Making Hardware Design Great Again in 2017
Ok, I admit it… that title is a blatant attempt to grab your attention. But it should also make you think. As a hardware designer, is your job great? Is it what you thought you’d be doing when you...
View ArticleClik here to view.
Making Hardware Design Great Again in 2017 - Part Deux
In part one of this series, we talked about the role of the hardware designer, specifically comparing the ideal version of the hardware designer with the real-world version. From the emails I received,...
View ArticleClik here to view.
“Great” Hardware Design in a Wireless World
As part three of the “Making Hardware Design Great Again” series, let’s see how high-level synthesis (HLS) is helping designers create SoCs for WiFi, Bluetooth, and 5G.A common challenge in all three...
View ArticleClik here to view.
Designing for Low Power… Begin at the Beginning
So you have your RTL written, and it’s time to optimize to reduce power. If that’s your plan, you are likely leaving power on the table. It’s not that you can’t get a lot of savings with existing RTL...
View ArticleClik here to view.
2017 Annual HLS Survey Results
As many of you know, Cadence (more correctly, “I”) recently performed an industry survey about HLS (High Level Synthesis) to get a fuller view of the productivity experiences and expectations from...
View ArticleClik here to view.
A new Electrostatic Discharge Analysis Solution – You Will Never Get Zapped!
“It’s not what it is, it’s about what it can become”-The Lorax by Dr. SeussHave you recently reached out to open your car and received an unexpected shock…zap! There are no financial or health...
View ArticleClik here to view.
HLS Optimizations You Can't Do By Hand
In my previous blog post, I talked about the Quality-of-Results (QoR) that are achievable using High-Level Synthesis tools like Stratus HLS and the fact that exploration of multiple RTLL architectures...
View ArticleClik here to view.
LIBERATE 19.2 Base Release Now Available
The LIBERATE 19.2 production release is now available for download at Cadence Downloads. For information about supported platforms, compatibility with other Cadence tools, and details of key issues...
View ArticleClik here to view.
Designing for Low Power… Begin at the Beginning
So you have your RTL written, and it’s time to optimize to reduce power. If that’s your plan, you are likely leaving power on the table. It’s not that you can’t get a lot of savings with existing RTL...
View ArticleClik here to view.
2017 Annual HLS Survey Results
As many of you know, Cadence (more correctly, “I”) recently performed an industry survey about HLS (High Level Synthesis) to get a fuller view of the productivity experiences and expectations from...
View ArticleClik here to view.
Faster and Smarter
At the Cadence VIP dinner at Korea CDNLive last month, Paul Cunningham spoke about the state of the EDA industry, especially in the digital and signoff world.It all comes down to the productivity gap...
View ArticleClik here to view.
Functional Correctness—The Forgotten Benefit of HLS
I like to ask questions, because you learn a lot that way. In fact, I did a survey earlier this year and learned that high-level synthesis users’ experiences are exceeding the non-users’ expectations,...
View ArticleClik here to view.
Cadence Modus DFT at International Test Conference 2017
While DAC is the focal point for the EDA industry, the test community travels in a slightly separate orbit. There are many conferences throughout the year, and around the globe, to help bridge the...
View ArticleClik here to view.
Need Help with Liberate Commands and Parameters?
Alexa, what is square root of 12547858?Within some nanoseconds, Alexa gives you the answer to it. That's how convenient technology has made things for us! How cool would it be if Alexa could get some...
View ArticleClik here to view.
Exploring AI / Machine Learning Implementations with Stratus HLS
A lot of AI design is done in software and, while much of it will remain there, increasing numbers of designs are finding their way into hardware. There are multiple reasons for this including the...
View ArticleClik here to view.
Faster and Smarter
At the Cadence VIP dinner at Korea CDNLive last month, Paul Cunningham spoke about the state of the EDA industry, especially in the digital and signoff world.It all comes down to the productivity gap...
View ArticleClik here to view.
Functional Correctness—The Forgotten Benefit of HLS
I like to ask questions, because you learn a lot that way. In fact, I did a survey earlier this year and learned that high-level synthesis users’ experiences are exceeding the non-users’ expectations,...
View ArticleClik here to view.
Cadence Modus DFT at International Test Conference 2017
While DAC is the focal point for the EDA industry, the test community travels in a slightly separate orbit. There are many conferences throughout the year, and around the globe, to help bridge the...
View Article