ECO with Stratus HLS and the Digital Implementation Flow

For years chip designers have dealt with ECO’s when their source code was written in RTL. But the move to high-level synthesis (HLS) means that their source code is now one step further removed from the gate level netlist. This naturally leaves a question, “What if I need an ECO on my Stratus  project?”

First and foremost, it’s important to understand that ECO’s are less common in the HLS flow. I’ll explain why in a follow-on article, but for now let’s focus on the question at hand… “What if I need an ECO on my Stratus project?”

Two categories of ECO

Not all ECO’s are created the same, and not everyone means the same thing when they ask that question. Broadly, there are two types of ECO’s.

In one type, which we’ll call “top-down,” the ECO is initiated with a change to the designer’s code after the RTL, gate-level netlist, or even layout is frozen. The goal is to minimize the perturbation on the downstream flow after making the change. These are typically, but not always, functional changes due to errors caught in verification or changes to the spec.

The other type, which we’ll call “bottom-up” (shocking, I know), the ECO is initiated with a change to the netlist, pre-or post-layout. The goal is to reflect the change in the designer’s code, so it stays in sync with the changed netlist. These tend to be very late (and small) functional changes or timing-related changes.

Both types of ECO’s exist regardless of whether designing in RTL or in SystemC with HLS. But it is true there is a difference when designing with SystemC®… the ECO must be propagated one more level of abstraction than before.

Fortunately, Cadence has developed solutions to assist with doing ECO’s.

• Conformal® ECO Designer can take a changed RTL description and, working with Genus  Synthesis, create a netlist patch.
• Tempus works with Innovus and Voltus to automatically detect and fix timing errors on a routed netlist, including those caused by IR drop.
• And finally, Stratus HLS can provide minimally changed RTL in its top-down ECO mode, and help to reflect bottom-up ECO’s into your original SystemC.

Here, I’ll focus specifically on the ECO flows when the block being ECO’ed was created with HLS. If you are interested in Cadence’s other ECO flows, look at the excellent Rapid Adoption Kits and Application Notes available on the Cadence support site (login required).

Top-down ECO with Stratus HLS

The top-down ECO flow, where a small SystemC ECO is propagated to a small netlist change, involves a tight integration and flow between the Stratus HLS, Genus Synthesis, and Conformal ECO Designer solutions.

It all starts with the designer making a small change in the SystemC code. Then, Stratus HLS is run in its ECO mode, which prioritizes similarity with the pre-ECO design over area optimization. Next, Conformal LEC is used to determine which RTL module(s) have changed in the ECO’ed RTL. Finally, the changed modules go through the same process as an ECO with hand-written ECO, which involves Genus and Conformal working closely together to create the netlist patch.

This process is detailed in our new Rapid Adoption Kit, “Stratus HLS ECO Example” (login required), available in the Stratus Learning Center on the Cadence support site. It includes a more detailed Application Note and a tarball containing an example and all scripts needed to run it.

Bottom-up ECO with Stratus HLS

In a bottom-up ECO, the ECO change is initiated by hand-modifiying the netlist, and then propagated up to the RTL and SystemC. The process of propagating the netlist change to RTL is unchanged from an ECO in the handwritten RTL flow. However, because the original source code was SystemC, often the change is propagated to the SystemC, as well.

To aid in that, the Stratus design database contains, among other things, bi-directional mappings between the RTL and SystemC. Using the Stratus IDE, the designer can select the changed RTL and ask the IDE to show the corresponding SystemC. This information is also available via a full-fetaured Tcl API, if you don't prefer to use a GUI.

With the mapping in hand, the designer can easily propagate the change to SystemC and verify that it works as expected after the ECO change.

Parting thoughts

In my 20-year experience with HLS experience, I’ve seen that ECO’s are less frequent for projects done with HLS compared to hand-written RTL. As I mentioned before, I’ll discuss some reasons for that in a future article.

Regardless, there are times when an ECO is required, and we have a proven solution that can help. Taken together, the Stratus, Conformal, Stratus, Genus and Innovus solutions, running in ECO mode, can greatly simplify the process of implementing ECO's.