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Do You Want to Explore Instances in Genus Synthesis Solution Layout GUI?
What comes to your mind when we say Genus Layout GUI (Graphical User Interface)? You picture the floorplan filled with instances and objects. Imagine you need to highlight the specific instance or...
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Chris, Kris, Cris, Your Name, My Name; Does How You Spell the Name Matter to...
No matter how your name is spelt in different countries, and how they say it, once they get to know you, people identify you as the same person.Ah! this is Chris, Cris, Kris, Kirshner, or Krishna. And...
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Are You Planning To Synthesize Your Design? Do You Want To Explore the...
A Logic Synthesis is a process of optimizing the design's area, timing, and power.You might be a beginner in the synthesis world, but we can help you sail through it smoothly. It's time to introduce...
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Power Is HOT and Touches Everything and Everybody! But the Challenge Is To...
Low-Power synthesis is one of the important stages in the full IC flow. Here, you synthesize the design from behavioral description to gates while optimizing for dynamic and leakage power using various...
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Do you want to Flaunt your Expertise? Grab the Digital Badge Today!
When you achieve the credit for proficiency, do you want to show it to the world?We know it isn’t easy to carry the actual physical badge (certificate) everywhere today. Why? Expenses, pandemic, making...
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Scan Mapping, Expectation Versus Reality? It's Time to Grab All the Scan Cells!
We all look for 100% perfection and want to turn our dreams (expectations) into reality as far as we can. Are you also looking for a magic wand to turn expectation into reality?The story applies to DFT...
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Chris, Kris, Cris, Your Name, My Name; Does How You Spell the Name Matter to...
No matter how your name is spelt in different countries, and how they say it, once they get to know you, people identify you as the same person.Ah! this is Chris, Cris, Kris, Kirshner, or Krishna. And...
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Voltus Voice: Overcoming Design Challenges Using Voltus Documentation—The...
This post facilitates easy access to the Voltus Help and Documentation through the most useful resources from the Cadence support and corporate websites directly from the tool interface.(read more)
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Training Insights - Achieving a Holistic Power-Aware Design by Getting...
This blog post mentions the Cadence Low Power Solution, a design-to-signoff methodology, that helps you implement several low-power techniques to reduce both dynamic and leakage power during synthesis...
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What's Behind the 5% Die-Area Shrink and 12% Power Saving by MediaTek?
Leveraging Cadence Cerberus AI-Enabled Chip Optimization Solution MediaTek Achieves Transformative PPA and Improved ProductivityThe semiconductor industry is in the midst of a global renaissance. With...
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Voltus Voice: Playback 2021 - Power Integrity Blogs At a Glance
A recap of the power integrity posts in the Voltus Voice blog series through 2021. (read more)
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RTL-to-GDSII Flow: I Am Not a Tool but Can Help You Implement Your Entire...
Passion motivates and helps you pursue it further, but gaining expertise requires time and effort. For example, photography is a popular hobby because anyone can take a picture. But to gain expertise...
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What's Behind the 5% Die-Area Shrink and 12% Power Saving by MediaTek?
Leveraging Cadence Cerberus AI-Enabled Chip Optimization Solution MediaTek Achieves Transformative PPA and Improved ProductivityThe semiconductor industry is in the midst of a global renaissance. With...
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Brain on Fire - AI/ML Art Creation
No matter how you feel about the topic, we're definitely past the turning point in history where most humans interact with machines much more than other humans.Advancements in artificial intelligence...
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Voltus Voice: Five Great Features to Enhance Your Full-Chip Power Signoff
This blog shares five great features to unlock the potential of your digital designs and enhance full-chip power signoff.(read more)
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Training Insights – Design Robustness Analysis Application: Aging-Aware STA
This blog post describes the phenomenon of Aging, the factors affecting it, and how Cadence solves this problem with its groundbreaking Aging-Aware STA technology enabled using Liberate, Spectre, and...
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SSV 22.1 Base Release Now Available
The Silicon Signoff and Verification (SSV) 22.1 release is now available for download.(read more)
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Resolve Congestion and Physical Design Challenges Using Cadence Support and RAKs
Physical design challenges such as congestion, routing, on-chip variation (OCV), and unconstrained paths are significant issues in achieving the design goals. Managing the routing congestion and...
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Relax in Summer with Cooler IC chips and Ice-Cream! Do you want to Explore...
Are you passionate about cooking? Err... Don't think it is a regular cooking class.Here we tend to cook cooler power solutions! Do you know creating a cooler IC chip is as easy as enjoying the...
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Voltus Voice: How to Find Functional Power Vectors that Matter Quickly
Vector profiling enables ASIC designers to quickly identify areas with maximum activity and power consumption when analyzing long simulation vectors, accelerating power signoff of billion-node designs....
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