Testing digital IC designs is crucial for several reasons, including cost savings, time efficiency, and the removal of inefficiencies. Testing is an essential step to ensure the accuracy and robustness of modern chips. Despite its importance, there are several reasons why testing might not always be as thorough as it should be: one major reason is that your design is not testable.
The Cadence Test solution, with tight integration of Genus Synthesis Solution and Modus Test Solution, is an important piece of the digital platform to make the design testable. Its integration with our global one-pass synthesis leads to predictable results. The Cadence Test Solution:
- Leverages Genus infrastructure to insert, connect, and verify DFT logic.
- Leverages physical synthesis and power-aware infrastructure.
- Provides Test Point insertion flow to augment coverage.
- Interfaces to Modus DFT Software Solution for ATPG and diagnostics
The Cadence Test Solution is a complete flow, not a point solution.
Cadence Genus Synthesis Solution synthesizes the DFT inserted netlist by setting and running the DFT rule checker, fixing the DFT violations, improving the testability of the design, configuring, and connecting scan chains. DFT features in Genus Synthesis include:
- Checking DFT rules for scan chain creation
- Creating scan chain abstraction models
- Inserting shadow logic around untestable logic
- Analyzing logic for testability and inserting test points
- Configuring DFT constraints and connecting scan chains
- Inserting Boundary Scan
- Inserting PMBIST logic
- Inserting test Compression logic
- Inserting OPCG, 1500 Core Wrapper, LBIST
- Outputting scan DEF and ATPG interface files
All these test Synthesis features have complex interactions and interdependencies on each other.
To learn more about how to make your design testable by configuring and connecting scan chains by adding advance testability features (for ex: Boundary Scan, PMBIST, Compression, OPCG, and IEEE 1500 Wrapper) with Genus Synthesis Solution, you can take the online course Test Synthesis with Genus Stylus Common UI Trainingv23.1.
In the Test Synthesis with Genus Stylus Common UI Trainingv23.1 course, you will learn to:
- Constrain the design for testability (DFT)
- Run the DFT rule checker and fix DFT violations
- Synthesize the design and map to scan
- Set up DFT configuration constraints and preview scan chains
- Connect scan chains
- Run hierarchical scan insertion
- Troubleshoot scan issues
- Run advanced testability features, boundary scan, PMBIST, Compression, OPCG, and IEEE 1500 wrapper
Register for the Online Training with the following steps:
- Log on to Cadence.com with your registered Cadence ID and password
- Select Learning from the menu > Online Courses
- Search for "ATPG Flow with Modus DFT Software Solution" using the search bar
- Select the course and click "Enroll”
After completing the online training, Cadence Training Services offers a Digital Badge to showcase your expertise in the training. Once you get the Digital Badge, you can add this to your email signature or any social media platform, such as Facebook or LinkedIn, to highlight your expertise.
