New Training Bytes Available: "What Is Mapping?" and “What Is Comparison?”
Equivalence checking is a formal verification technique used to prove that two designs behave identically. It's particularly useful in electronic design automation (EDA) for designing integrated circuits. Here's a breakdown of the comparison process:
- Setup: Two designs are loaded into the equivalence checker. One is usually a verified "golden" model, and the other is a modified version.
- Mapping: The checker automatically identifies corresponding points in both designs. This can involve matching elements, signals, and functionality between the two.
- Comparison: The identified points are compared to determine if their behavior is equivalent. This may involve analyzing logic functions, signal values, and timing characteristics (depending on the type of equivalence checking being done).
The checker will report any discrepancies between the designs. These could be actual errors or may require further analysis depending on the intent of the modifications.
Equivalence checking offers several advantages over traditional simulation-based methods. It's generally faster and more efficient as it doesn't rely on running extensive test cases. It also provides a more formal guarantee of equivalence between designs.
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What Next?
Join the Conformal Equivalence Checking 23.1 training and learn more about:
- Use Conformal logic equivalence checking for flat and hierarchical design comparison
- Read libraries and designs
- Apply design constraints and modeling directives
- Apply the mapping process and debug unmapped key points
- Apply the compare process and debug non-equivalent points
The online class is free for all Cadence customers with a Cadence Learning and Support Portal account. If you don’t have a Cadence Support account, go to Registration Help or Register Now and complete the requested information. For instructor-led training sessions "Live" or "Blended" please contact Cadence Training.
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