Clik here to view.
Voltus Voice: Demystifying ESD – Touch Ground with a Designer-Centric...
This blog highlights the key capabilities and benefits of the Voltus ESD analysis flow.(read more)
View ArticleClik here to view.
Library Characterization Tidbits: Accelerating Signoff with Liberate -...
This is the second edition of the Library Characterization Tidbits' mini-series that shares insights into the questions that our customers frequently ask. Here, we continue with Part 2 of questions...
View ArticleClik here to view.
Voltus Voice: Amplifying Your Chip Performance and Reliability to Solve...
This blog introduces the new cloud-ready Extensively Parallel (XP) solution from Voltus IC Power Integrity Solution that allows designers to analyze massive designs in record time, distributing tasks...
View ArticleClik here to view.
Library Characterization Tidbits: Rewind and Replay - 3
This blog provides a summary of the last five blogs posted in the Library Characterization Tidbits blog series.(read more)
View ArticleClik here to view.
It May Sound Unbelievable, But Do You Know You Can Relax While Analyzing...
Gone are the days when analyzing timing reports of the design used to take hours! We understand, your designs are complex and so is timing analysis. We cannot change the design, but we have made the...
View ArticleClik here to view.
Voltus Voice: Demystifying ESD – Touch Ground with a Designer-Centric...
This blog highlights the key capabilities and benefits of the Voltus ESD analysis flow.(read more)
View ArticleClik here to view.
Library Characterization Tidbits: Accelerating Signoff with Liberate -...
With this blog starts a mini-series in Library Characterization Tidbits to share insights into the questions that our customers frequently ask. In this first edition, read about questions related to...
View ArticleClik here to view.
Use the Industry’s Leading Digital Implementation Flow from inside Virtuoso...
Hi Everyone, Does the idea of using the best digital implementation tools on the market for your block sound interesting to you, but the full capacity is overkill, setup too daunting, or costs too...
View ArticleClik here to view.
Voltus Voice: Tempus Power Integrity Solution - Find Those Needles in the...
This blog introduces the Tempus Power Integrity Solution that integrates the Tempus Timing Signoff Solution and Voltus IC Power Integrity Solution signoff engines to find silicon performance failures...
View ArticleClik here to view.
Innovus Design Metrics: Visualize This!
To arrive at your targeted and optimized PPA, you will need to execute several Innovus runs with a variety of design parameters, commands, and options.You will then need to analyze the data which could...
View ArticleClik here to view.
Voltus Voice: Worried about Fins Getting Self-Heated – Here’s SHE Analysis to...
This blog highlights the key capabilities of the Voltus Self-Heat Effect (SHE) analysis flow. (read more)
View ArticleClik here to view.
Wondering What to Do During the Winter Staycation? How about Learning...
We just recently released a training course that we are excited to tell you about.The course is RTL-to-GDSII Flow.This course is unique in that it takes a tiny design through a wide variety of Cadence...
View ArticleClik here to view.
Do You Know Multibit Cells Could Help You Reduce Clock-Tree Power and...
Hi everyone,Searching for yet another method to improve the QoR of your design? What about taking advantage of the improvements in area and power that the Multibit Cell Inferencing (MBCI) flow...
View ArticleClik here to view.
Library Characterization Tidbits: Bidding Adieu to 2020
This year all our “regular” routines were shaken up by COVID-19, which brought along many challenges for people all over the world. (read more)
View ArticleClik here to view.
Voltus Voice: Power Integrity and Signoff in 2020 – A Jog Down Memory Lane
VoltusTM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the...
View ArticleClik here to view.
All you need to know about Application Engineering in EDA
"How many tape-outs have you done?"asked the design manager of a semiconductor company. My colleague and I were on a call with him to walk him through an implementation training agenda. He further...
View ArticleClik here to view.
Library Characterization Tidbits: Recovering from Failures in the Multi-PVT...
Ever wondered what should you do if any arc, cell, or PVTs failed in a characterization run? Do you need to rerun the entire characterization process? Certainly not if you know about how to use the...
View ArticleClik here to view.
Voltus Voice: Power-Saving Chip Design Is Not a Choice; It’s a Necessity
A blog on how the Voltus power-gating analysis solution enables engineers to address the low-power design challenge of extending battery life while reducing the leakage power.(read more)
View ArticleClik here to view.
Understanding Clock Gating Report and Cells
Hi everyone, Are you interested in reducing the power dissipation of your design? Who wouldn’t? What about taking the advantage of Clock Gating? Clock Gating is a technique that enables inactive...
View ArticleClik here to view.
Library Characterization Tidbits: Importance of Noise Analysis and the Role...
The hustle bustle of the cities is only an example of the external noise, which we are aware of through the obvious observations of our sensory organs. However, in terms of electronics, a noise maybe...
View Article