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Genus Synthesis Solution – Introduction to Stylus Common UI
The Cadence® Genus Synthesis Solution, Innovus Implementation System, and Tempus Timing Signoff Solution have a lot of shared functionality, but in the past, the separate legacy user interfaces...
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Exploring Genus-Joules Integration is just a click away!!
Joules RTL Power Solution provides a cockpit for RTL designers to explore and optimize the power efficiency of their designs. But this capability is now not just limited to RTL designers!! Yes, you as...
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Joules – Power Exploration Capabilities
Several tools can generate power reports based on libraries & stimulus. The issue is what's NEXT?Is there any scope to improve power consumption of my design?What is the best-case power?Pin-point...
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Library Characterization Tidbits: Rewind and Replay
A recap of the blogs published in the Library Characterization Tidbits blog series.(read more)
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Voltus Voice: Power Signoff Ramp-Up RAKs – Hello Electrical, Meet Thermal!
This blog introduces the Voltus-Celsius Electro-Thermal Analysis RAK that will give you an accelerated start to achieve accurate co-analysis of a power-grid network on a chip-package-PCB system.(read...
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Liberate Characterization Tidbits: Deconstructing the Mechanics of Liberate...
Thinking about how Liberate MX characterizes the constraint arcs, how the probe locations are picked up by the tool, what are the various controls associated with probing? Read the blog to find the...
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It May Sound Unbelievable, But Do You Know You Can Relax While Analyzing...
Gone are the days when analyzing timing reports of the design used to take hours! We understand, your designs are complex and so is timing analysis. We cannot change the design, but we have made the...
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Voltus Voice: Demystifying ESD – Touch Ground with a Designer-Centric...
This blog highlights the key capabilities and benefits of the Voltus ESD analysis flow.(read more)
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Library Characterization Tidbits: Accelerating Signoff with Liberate -...
With this blog starts a mini-series in Library Characterization Tidbits to share insights into the questions that our customers frequently ask. In this first edition, read about questions related to...
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Use the Industry’s Leading Digital Implementation Flow from inside Virtuoso...
Hi Everyone, Does the idea of using the best digital implementation tools on the market for your block sound interesting to you, but the full capacity is overkill, setup too daunting, or costs too...
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Voltus Voice: Tempus Power Integrity Solution - Find Those Needles in the...
This blog introduces the Tempus Power Integrity Solution that integrates the Tempus Timing Signoff Solution and Voltus IC Power Integrity Solution signoff engines to find silicon performance failures...
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Library Characterization Tidbits: The Perfect Solution for Validating Libraries
A library view contains electrical information that is used throughout design implementation starting from logic synthesis through design optimization to the final signoff verification. (read more)
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Join Us for a Deep-Dive into Block Implementation with Innovus Using the...
If you are looking for a comprehensive training on block implementation with Innovus using the Stylus Common User Interface, look no further. This 3-day training, suitable for both beginner- and...
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Voltus Voice: Accelerate Power Signoff and Design Closure with this IR Aware...
This blog introduces the Innovus Power Integrity Solution that integrates the Innovus Implementation System and Voltus IC Power Integrity Solution to alleviate signoff bottlenecks and provide faster...
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A Refresher on the Basics of Timing Analysis and Signoff
Technology is changing the strategies we use to do things - oh so fast that 2010 seems like a distant past- within many spaces -- including the way we do our current topic of interest - Timing Signoff...
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What’s inside Joules Graphical User Interface!!
Power is HOT and it touches everything and everybody! But we can help with power analysis for your chip!!Do you want to:Sneak peek inside the schematic?Analyze power for various blocks?Identify the...
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Library Characterization Tidbits: Characterize Minimum Period for Memory...
In this blog, I will talk about the minimum period arc, which is a critical arc associated with the clock of a memory instance.(read more)
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Voltus Voice: Accelerate Power Signoff and Design Closure with Targeted Local...
This blog is in continuation with the post on the IR-Aware placement technology that is used at the early design stage to mitigate IR drop hotspots and ease final signoff. The second part of this blog...
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Library Characterization Tidbits: Deconstructing the Mechanics of Liberate MX...
Thinking about how Liberate MX characterizes the constraint arcs, how the probe locations are picked up by the tool, what are the various controls associated with probing? Read the blog to find the...
View ArticleClik here to view.
It May Sound Unbelievable, But Do You Know You Can Relax While Analyzing...
Gone are the days when analyzing timing reports of the design used to take hours! We understand, your designs are complex and so is timing analysis. We cannot change the design, but we have made the...
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