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Voltus Voice: Demystifying ESD — Four Simple Steps to Run ESD Analysis...
This blog post outlines four simple steps for analysis of your electrostatic discharge (ESD) protection circuitry using the Voltus ESD Analysis solution.(read more)
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Library Characterization Tidbits: Accelerating Signoff with Liberate -...
This is the second edition of the Library Characterization Tidbits' mini-series that shares insights into the questions that our customers frequently ask. Here, we continue with Part 2 of questions...
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Voltus Voice: Amplifying Your Chip Performance and Reliability to Solve...
This blog introduces the new cloud-ready Extensively Parallel (XP) solution from Voltus IC Power Integrity Solution that allows designers to analyze massive designs in record time, distributing tasks...
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Library Characterization Tidbits: Rewind and Replay - 3
This blog provides a summary of the last five blogs posted in the Library Characterization Tidbits blog series.(read more)
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Innovus Design Metrics: Visualize This!
To arrive at your targeted and optimized PPA, you will need to execute several Innovus runs with a variety of design parameters, commands, and options.You will then need to analyze the data which could...
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Voltus Voice: Worried about Fins Getting Self-Heated – Here’s SHE Analysis to...
This blog highlights the key capabilities of the Voltus Self-Heat Effect (SHE) analysis flow. (read more)
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iSpatial: Next-Generation Common Physical Optimization Flow
With advanced-process nodes, a standard cell's physical delay, net delay, and congestion all lead to a higher netlist requirement. Genus/Innovus iSpatial bridges synthesis and implementation with...
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Library Characterization Tidbits: Define Measurements to Suit Your...
Do you have a requirement to specify measurements that are not default while performing memory characterization? Liberate MX has a solution for you.(read more)
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Verifying Design Changes Does Not Have to Be Difficult and Tedious — Make It...
You put your design through a multitude of tools for various transformations. Going back to formal verification in between every change to rely on your simulation tools can be a rigorous approach, but...
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Voltus Voice: Demystifying ESD — 5 Types of Checks to Bump up Your ESD...
This blog discusses the different Voltus electrostatic discharge (ESD) checks in the form of rules to ensure your design is protected against ESD.(read more)
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Low-Power Implementation Training Videos
Hello Digital Designers,Interested in learning more about how to implement a low-power design?Do you have multiple voltage islands that need level-shifting, and isolation, and also require a CPF or...
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What’s Inside the GUI-Based Timing Report in Genus? Want to Explore?
Timing closure is one of the most crucial steps of a digital design. Therefore, to meet timing at the later stages of design signoff, it is imperative to consider timing analysis within the synthesis...
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Do You Know DFT Violations Can Be Debugged Using Genus GUI? Excited to Explore?
Design for Test (DFT) techniques provide measures to comprehensively test the manufactured device for quality and coverage. During the synthesis stage, you might encounter DFT violations that need to...
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Voltus Voice: Demystifying ESD—Charting Your Way through Voltus ESD Reports
In the concluding blog of our "Demystifying ESD" series, we walk you through the features of the Voltus Electrostatic Discharge (ESD) analysis reports that provide a clear insight on your design's...
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Voltus Voice: Power Integrity and Signoff in 2020 – A Jog Down Memory Lane
VoltusTM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the...
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All You Need to Know about Application Engineering in EDA
"How many tape-outs have you done?"asked the design manager of a semiconductor company. My colleague and I were on a call with him to walk him through an implementation training agenda. He further...
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Library Characterization Tidbits: Recovering from Failures in the Multi-PVT...
Ever wondered what should you do if any arc, cell, or PVTs failed in a characterization run? Do you need to rerun the entire characterization process? Certainly not if you know about how to use the...
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Voltus Voice: Power-Saving Chip Design Is Not a Choice; It’s a Necessity
A blog on how the Voltus power-gating analysis solution enables engineers to address the low-power design challenge of extending battery life while reducing the leakage power.(read more)
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Understanding Clock Gating Report and Cells
Hi everyone, Are you interested in reducing the power dissipation of your design? Who wouldn’t? What about taking the advantage of Clock Gating? Clock Gating is a technique that enables inactive...
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Have You Encountered Any Error/Warning During Scan Insertion in Genus? Do You...
Design for Test (DFT) techniques provide measures to test the manufactured device for quality and coverage comprehensively. You might encounter Error or Warning messages while inserting scan during the...
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