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Voltus Voice: Demystifying ESD – Touch Ground with a Designer-Centric Protection Scheme
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Library Characterization Tidbits: Accelerating Signoff with Liberate - Installation and Licensing - Part 2
This is the second edition of the Library Characterization Tidbits' mini-series that shares insights into the questions that our customers frequently ask. Here, we continue with Part 2 of questions related to installation, configuration, and licensing of the Cadence Liberate Characterization solution.(read more)![]()
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Voltus Voice: Amplifying Your Chip Performance and Reliability to Solve Big-Data Challenges
This blog introduces the new cloud-ready Extensively Parallel (XP) solution from Voltus IC Power Integrity Solution that allows designers to analyze massive designs in record time, distributing tasks among thousands of CPUs while seamlessly processing terabytes of data.(read more)![]()
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Library Characterization Tidbits: Rewind and Replay - 3
This blog provides a summary of the last five blogs posted in the Library Characterization Tidbits blog series.(read more)![]()
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It May Sound Unbelievable, But Do You Know You Can Relax While Analyzing Timing Results in Genus? Want to Check?
Gone are the days when analyzing timing reports of the design used to take hours! We understand, your designs are complex and so is timing analysis. We cannot change the design, but we have made the timing analysis process easier for you during the synthesis stage.
Are you ready to relax? Stop at channel-based Training Bytes on “Useful scripts for Timing Report Analysis” at https://support.cadence.com (Cadence login required).
This channel contains a series of videos that will walk you through various example scripts that can be used for timing report analysis. The examples show various options and combinations of reporting timing in the form of script or procedure to analyze slack, fan in, fanout, paths, pins, etc..
Video Link: Usefulscripts for TimingReportAnalysis (Channel Video)
Related Resources:
Enhance the Genus Synthesis Solution experience with videos: Genus Synthesis Solution: Video Library
For any questions, general feedback, or future blog topic suggestions, please leave a comment.
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Voltus Voice: Demystifying ESD – Touch Ground with a Designer-Centric Protection Scheme
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Library Characterization Tidbits: Accelerating Signoff with Liberate - Installation and Licensing - Part 1
With this blog starts a mini-series in Library Characterization Tidbits to share insights into the questions that our customers frequently ask. In this first edition, read about questions related to installation, configuration, and licensing of the Cadence Liberate Characterization solution. (read more)![]()
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Use the Industry’s Leading Digital Implementation Flow from inside Virtuoso with a Package Sized and Priced Perfect for Your Next Mixed Signal Project!
Hi Everyone,
Does the idea of using the best digital implementation tools on the market for your block sound interesting to you, but the full capacity is overkill, setup too daunting, or costs too high?
If the answer is yes, do not worry; Cadence has...(read more)![]()
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Voltus Voice: Tempus Power Integrity Solution - Find Those Needles in the Haystack Quickly!
This blog introduces the Tempus Power Integrity Solution that integrates the Tempus Timing Signoff Solution and Voltus IC Power Integrity Solution signoff engines to find silicon performance failures missed with traditional IR analysis.(read more)![]()
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Innovus Design Metrics: Visualize This!
To arrive at your targeted and optimized PPA, you will need to execute several Innovus runs with a variety of design parameters, commands, and options.
You will then need to analyze the data which could mean wading through several log files and timing reports, a time-consuming task at best.
To make it easier to visualize the data by generating an easy-to-read dashboard, Innovus now has integrated metrics commands. These commands display PPA numbers at various stages of the implementation flow as well as allow you to compare metrics for several runs. The HTML dashboard report provides useful and user-friendly data to optimize your design further.
This video demo shows you how to use the metrics commands in Innovus and also contains an example of what the output looks like.
Note: The demo is based on the default mode of Innovus and not on the Stylus mode of Innovus Stylus.
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Voltus Voice: Worried about Fins Getting Self-Heated – Here’s SHE Analysis to the Rescue
This blog highlights the key capabilities of the Voltus Self-Heat Effect (SHE) analysis flow. (read more)![]()
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Wondering What to Do During the Winter Staycation? How about Learning Something New?
We just recently released a training course that we are excited to tell you about.
The course is RTL-to-GDSII Flow.
This course is unique in that it takes a tiny design through a wide variety of Cadence tools so that you can gain some exposure to tools that you may not be familiar with.
You learn how to implement a design from RTL-to-GDSII using Cadence tools. You will start by learning how to code a design in VHDL or Verilog. You will simulate the coded design, followed by design synthesis and optimization. You will then run equivalency checks at different stages of the flow. After synthesizing the design, you will floorplan, and place-and-route the synthesized netlist while meeting timing. You will run gate-level simulation throughout the flow. Finally, you will write out a GDSII file.
Tools include:
- Xcelium Simulator (XCELIUM2009)
- Genus Synthesis Solution (GENUS191)
- Cadence Modus DFT Software Solution (MODUS191)
- Conformal Equivalence Checker (CONFRML201)
- Innovus Implementation System (INNOVUS201)
- Tempus Timing Signoff Solution (SSV201)
- Voltus Power Signoff Solution (SSV201)
- Quantus RC Extraction (SSV201)
If you are affiliated with a university, you can request access to Cadence software, this training course, and all of our training courses via our Cadence Academic Network Program.
Happy Holidays and Happy Learning!
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Do You Know Multibit Cells Could Help You Reduce Clock-Tree Power and Alleviate Wiring Congestion in the Clock Path?
Hi everyone,
Searching for yet another method to improve the QoR of your design? What about taking advantage of the improvements in area and power that the Multibit Cell Inferencing (MBCI) flow provides?
Merging to multibit cells refers to the merging of the individual register bits from the same or different bus into multibit cell instances. That way, a single clock pin can be used to trigger all register bits in the multibit cell. Hence, the clock-tree synthesis becomes easier, since both the number of clock nets to be routed and the number of register endpoints to be considered when balancing the clock-tree are reduced. As a result, for a similar external clock pin capacitance, the cell clock port drives internally more than one DFF, reducing the number of sinks for the clock tree. This means fewer clock tree elements, which leads to a reduction of the clock-tree power and alleviation of the wiring congestion in the clock path.
Read through this article to get answers to your questions like:
What is multibit merging? Why is it needed?
How to locate multibit libcells?
How is a multibit cell defined in the library?
How to control the default multibit merging behavior of Genus?
If this idea sounds appealing but all that extra information in the report files seems daunting and hard to interpret, relax! Cadence has you covered with the Training Byte about “How to Analyze the Multibit Cell Report in Genus Synthesis Solution”. This Training Byte will guide you through the settings you need to get all the important information from the report, like the number of the merged instances, the percentage of the multibit conversion, and even the reasons why certain single bit cells are not merged into multibit. Furthermore, it will answer questions regarding how the cells get merged, what should be the actual target for MBCI (Multi Bit Cell Inference), and how this will affect the place and route later. So, follow us with the material below and make the most out of the Multibit Cell Report in Genus Synthesis Solution in the most convenient way!
Enhance the Genus Synthesis Solution experience with more videos: Genus Synthesis Solution: Video Library .
Note: For lab instructions and a downloadable design please enroll in the corresponding trainings like Genus Synthesis Solution v19.1 (Online).
The above links are accessible only to Cadence customers who have a valid login ID for the Cadence Learning & Support Portal.
Don´t have an account right now?
- On theLearning and Support portal go to Registration Help, select Register Now and complete the requested information.
- You will need an email address and hostID in order to sign up.
- If you need help with registration, contactsupport@cadence.com.
All classes can also be delivered as Instructor-led Training and – important for the current situation - also as Blended Training. Do you have questions about courses, schedules, online, public, blended or onsite training? Then reach out to us at Cadence Training.
Become Cadence Certified
Cadence Training Services now offers digital badges for this training course. These badges indicate proficiency in a certain technology or skill and give you a way to validate your expertise to managers and potential employers. You can highlight your expertise by adding these digital badges to your email signature or any social media platform, such as Facebook or LinkedIn. Get Cadence Certified. Please find further information here .
To stay up to date with the latest news and information about Cadence training and webinars subscribe to Cadence Training emails.
Mukesh Jaiswal
Sr. Knowledge Manager (Digital and Signoff)
On behalf of the Cadence Learning and Support team
Related Posts:
Innovus Implementation System: What Is Stylus UI?
Exploring Genus-Joules Integration is just a click away!!
Are You Struggling to Meet the Timing for Your Design? Stop Worrying!
Are You Stuck While Synthesizing Your Design Due to Low-Power Issues? We Have the Solution!
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Library Characterization Tidbits: Bidding Adieu to 2020
This year all our “regular” routines were shaken up by COVID-19, which brought along many challenges for people all over the world. (read more)![]()
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Voltus Voice: Power Integrity and Signoff in 2020 – A Jog Down Memory Lane
VoltusTM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.
Aside from my cuppa, the other ritual that is now part of my morning routine is glancing through the Rediscover this Day and Memories features of Google Photos. One of these nostalgic presentations that got me hooked is an amazing collage of my daughter that has curated visual memories of her childhood from being a toddler to a preschooler. No marks for guessing that the technology behind this feature is Artificial Intelligence that comprises machine learning and facial recognition. This technology has the capability to accurately detect the same individual across years and take you on a wonderful trip down memory lane. In the professional sphere similarly, VoltusTM IC Power Integrity Solution is already leveraging some of these highly innovative machine learning techniques to do our analytics (PPA, TAT, CPU), revolutionize our designs, and take up digital implementation challenges.
As we wind up 2020, there’s no better way than to revive and reminisce the blogging journey of Voltus Voice… let’s do a Rediscover blog post! Since this series’ inception in June 2020, we have published eight blogs from experts on a variety of key technology topics. Here is my version of “Rediscover this Series” narrative to give you a quick flashback of the different blog posts:
And in case you missed reading any of these posts, here are the links to what we published in 2020:
- A New Blog Series to Discover the “Power” Within
- Power Signoff Ramp-Up RAKs – Hello Electrical, Meet Thermal!
- Demystifying ESD – Touch Ground with a Designer-Centric Protection Scheme
- Tempus Power Integrity Solution - Find Those Needles in the Haystack Quickly!
- Accelerate Power Signoff and Design Closure with this IR Aware Placement Technology
- Accelerate Power Signoff and Design Closure with Targeted Local PG Addition
- Amplifying Your Chip Performance and Reliability to Solve Big-Data Challenges
- Worried about Fins Getting Self-Heated – Here’s SHE Analysis to the Rescue
Before you sign out from 2020 and go off-grid, we want to thank you for your readership and support of the Voltus Voice series this year. May you have a joyous, relaxing and refreshing holiday season! We’ll be back in 2021 with many more innovative features for delivering record performance in power signoff.
- Priya E. Joseph
About Voltus Voice
“Voltus Voice” showcases our product capabilities and features, and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.
Click Subscribe to visit the Subscription box at the top of the page in which you can submit your email address to receive notifications about our latest Voltus Voice posts.
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All you need to know about Application Engineering in EDA
"How many tape-outs have you done?"
asked the design manager of a semiconductor company. My colleague and I were on a call with him to walk him through an implementation training agenda. He further explained the intent of the question
“I am looking for trainer who has hands-on experience in implementing design. I want the training to be more design challenge oriented rather than just talking about command and switches”.
I found this to be an exact match for what we could offer. “Indeed. Application Engineers are involved in every single tape-out that has ever happened in our customer base. We are called upon when the challenges get really tough”, I replied. My colleague added, “As application engineers, we get to work on all kinds of designs, methodology, verticals and different nodes. This helps broaden our experience which in-turn benefits the designers with whom we collaborate”.
The inaccurate and yet common impression about application engineer (AEs) is that they support customers by unlocking some hidden switches to get around the problem faced while designing the integrated circuits (“chips” as they are commonly called)
Being an application engineer for 15 years, I gathered a few ways to “describe” this role to those who are not familiar with it
- One of the key interfaces of Cadence to customers
- Customer’s first technical touchpoint with the company
- The interface between R&D and customers
- The customer’s design methodology consultant and partner
While these are all part of the application engineering role, none of them can fully describe the role. The combination of all comes quite close but it’s still not complete. There is more to application engineering.
An Expert Design Consultant
When I graduated from my Master’s program, I aspired to build a career that allowed me to learn about the chip designing process for different end-applications like mobile, infotainment, graphics, etc. I imagined that I could become an expert consultant who would be called to solve tough problems. The beauty of being a consultant, as I imagined at that time, was that you are always solving some difficult problem without having to do the repetitive tasks.
For being a successful application engineer, one needs to bring in a great deal of technical domain knowledge. In fact, the depth of technical expertise will determine the success of an application engineer. After all, customers are looking for experts in the domain.
At the same time, an application engineer works with multiple customers doing different kinds of designs, etc. This provides an unparalleled learning opportunity.
Let me take an example. When an application engineer is consulted for design implementation flow, a wide variety of challenges needs to be solved. Most of these challenges are orthogonal. That way application engineer gets to work on those broad challenges at the same time. The opportunity to work on different design challenges for different methodology accelerates the learning process.
The exposure to different phases of design implementation and verification helps the AE comprehend the chip design process in a comprehensive way. By virtue of this role, one soon becomes what is commonly known as “full-flow” expert. The experience, thus gained puts the application engineer a step ahead of their peers in other roles in semiconductor companies. For this reason, very quickly AE becomes the trusted partners for solving challenging design problems.
An Empathetic Design Partner
The deep-rooted technical knowledge is one part of the role. The technical depth is necessary but not sufficient condition for being a successful application engineer. This role inherently also need good people skills. This is the only technical role that I know which demands good people skills early on in career.
An AE needs to interact with people from diverse backgrounds to understand their current challenges and future needs. Dynamic tuning of communication style is required on a daily basis. In my opinion this role needs a good mix of technical skills as well as good communication skills (listening with the intent to understand and asking right questions).
Good communication skills can also help to understand how the industry is evolving for next-gen innovation. Once understood, the application engineer can champion the cause and get tools future-ready. This, in my opinion, is the most significant contribution of an AE to technological advancement. Chip designing has been greatly enabled with one-step-ahead EDA tools.
Experience summarized
I have personally experienced a lot of transformation after joining as an application engineer. Recent college graduates who started their career as an application engineer would also have many personality transformational stories to narrate. Some say that their communication has improved, while others are honest about admitting that they have developed empathy to a great extent. These are life-skills that one gains by choosing to be an application engineer. These help in personal and professional life. Some say the exposure by doing hands on work in multiple verticals, and nodes has made them a strong solution consultant.
The satisfaction of being an enabler of the future of electronics is indescribable.
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Library Characterization Tidbits: Recovering from Failures in the Multi-PVT Characterization Flow
Ever wondered what should you do if any arc, cell, or PVTs failed in a characterization run? Do you need to rerun the entire characterization process? Certainly not if you know about how to use the recovery workflow in the multi-PVT characterization flow! Read more... (read more)![]()
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Voltus Voice: Power-Saving Chip Design Is Not a Choice; It’s a Necessity
A blog on how the Voltus power-gating analysis solution enables engineers to address the low-power design challenge of extending battery life while reducing the leakage power.(read more)![]()
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Understanding Clock Gating Report and Cells
Hi everyone,
Are you interested in reducing the power dissipation of your design? Who wouldn’t? What about taking the advantage of Clock Gating?
Clock Gating is a technique that enables inactive clocked elements to have gating logic automatical...(read more)![]()
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Library Characterization Tidbits: Importance of Noise Analysis and the Role that Liberate Plays
The hustle bustle of the cities is only an example of the external noise, which we are aware of through the obvious observations of our sensory organs. However, in terms of electronics, a noise maybe defined as any kind of unwanted signal that interferes with the real signal in a timing path in a cell or circuit. Modeling of accurate noise characteristics at the cell level and being aware of the possible failures early in the design cycle is of utmost importance to the designers. In this blog, let us explore answers to some key questions about noise characterization.(read more)![]()
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