In this training webinar, we explore the concepts of RTL design, design verification, and coverage analysis while unveiling the exciting world of front-end design flow. We will guide you through the essential steps in creating integrated circuits, the building blocks of modern electronics.

We’ll break down the process into manageable stages, from defining the chip’s functionality to its physical realization. We’ll investigate the front-end part of the RTL-to-GDSII flow—from specification to functional verification and design coverage—and explore:

• Key concepts of specifying chip behavior and performance
• How to translate ideas into a digital blueprint and transform that into a design
• How to ensure your design is free of errors

This webinar provides practical knowledge, making it your gateway to understanding the magic behind RTL-to-GDSII front-end design flow.

When Is the Webinar?

Date and Time

Wednesday, September 18, 2024
07:00 PDT San Jose / 10:00 EDT New York / 15:00 BST London / 16:00 CEST Munich / 17:00 IDT Jerusalem / 19:30 IST Bangalore / 22:00 CST Beijing 

REGISTER

To register for this webinar, sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System.

Then select Enroll to register for the session. Once registered, you’ll receive a confirmation email containing all login details.

If you don’t have a Cadence Support account, go to Cadence User Registration and complete the requested information. Or visit Registration Help.

For inquiries or issues with registration, reach out to eur_training@cadence.com.

For inquiries or issues with registration, reach out to eur_training@cadence.com.

To view our complete training offerings, visit the Cadence Training website.

Want to share this and other great Cadence learning opportunities with someone else? Tell them to subscribe.

Want to Learn More?

This link gives you more information about the related training course and a link to enroll:

Cadence RTL-to-GDSII Flow Training

The course includes slides with audio and downloadable laboratory exercises designed to emphasize the topics covered in the lecture. There is also a Digital Badge available for the training.

The online class is free for all Cadence customers with a Cadence Learning and Support Portal account. For instructor-led training sessions "Live" or "Blended" please contact Cadence Training.

Also, take this opportunity to register for the free Online Trainings related to this webinar topic.

Cadence RTL-to-GDSII Flow

Xcelium Simulator

Verilog Language and Application

Xcelium Integrated Coverage

Related Training Bytes

How to Run the Synthesis Without DFT?

How to Run the Synthesis Flow with DFT? (Video)

Related Blogs

Did You Miss the RTL-to-GDSII Webinar? No Worries, the Recording Is Available!

Training Insights – Why Is RTL Translated into Gate-Level Netlist?

Training Bytes: They May Be Shorter, But the Impact Is Stronger!

Cadence Support - A Round-the-Clock Problem Solver, Webinar Recording Available!

The traditional methods of power analysis lag by various shortcomings and challenges:

• Getting an accurate measure of RTL power consumption during design exploration
• Getting consistent power through the design progress from RTL to P&R.
• System-level verification tools are disconnected from the implementation tools that translate RTL to gates and wires.

The Cadence Joules RTL Power Solution closes this gap by delivering time-based RTL power analysis with system-level runtimes, capacity, and high-quality estimates of gates and wires based on production implementation technology. The Cadence Joules RTL Power Solution is an RTL power analysis tool that provides a unified engine to compute gate netlist power and estimate RTL power. The Joules solution delivers 20X faster time-based RTL power analysis and can analyze multi-million instance designs overnight, with impressive accuracy within 15% of signoff power.

Moreover, it integrates seamlessly with numerous Cadence platforms, eliminating compatibility and correlation issues! In addition, the Joules RTL Power Solution GUI (Graphical User Interface) helps you analyze/debug the power estimation/results using several GUI capabilities.

Want to take a tour of this power estimation world? Gear up to attend the training class created just for you to dive deep into the entire flow and explore this exciting power estimation method/flow with hands-on labs in two days!

Training

In the Joules Power Calculator Training course, you will identify solutions and features for RTL power using Cadence Joules RTL Power Solution. You will set up and run the RTL power flow with Joules RTL Power Solution and identify Joules's Graphical User Interface (GUI) capabilities. The training also explores how you can estimate power using vectorless power, stimulus flow, RTL Stim to Gate flow, and replay flow, and also interfaces Joules with Cadence's Palladium Emulation Platform. You will estimate power at the chip level and understand how to navigate the design and data mining using Joules.

The training also covers power exploration features and how to analyze ideal power and ODC-driven sequential clock gating. You will identify low-activity registers at the clock gate. You will also identify techniques to analyze power, generate various reports, and analyze results through Joules GUI. The training covers multiple strategies to debug low stimulus annotation and how you can better correlate RTL power with signoff. You also identify Genus-Joules Integration. In addition, we ensure that your learning journey is smooth with hands-on labs covering various design scenarios.

Lab Videos

To start you on your exciting journey as an RTL power analysis expert, we have created a series of short channel lab videos on our Customer Support site: Lab Demo: Setting Up and Running Basic RTL Power Flow in Joules RTL Power Solution (Video). You can refer to each lab module's instructions in demo format. This will help accelerate your tool ramp-up and help you perform the lab steps more quickly if you are stuck. You might be a beginner in the RTL power analysis world, but we can help you sail through it smoothly.

What's Next?

Grab your badge after finishing the training and flaunt your expertise!

Related Training

• Genus Low-Power Synthesis Flow with IEEE 1801
• Low-Power Synthesis Flow with Genus Stylus Common UI

Related Blogs

• Do You Want to Flaunt Your Expertise? Grab the Digital Badge Today!
• Become Cadence Certified
• Let's Replay the Process of Power Estimation with the Power of 'x'
• Let's Discover the Secret to Enhance Design's PPAC in a Single Cockpit
• What's Inside Joules Graphical User Interface
• Joules – Power Exploration Capabilities

Power efficiency is a critical factor in the fast-evolving world of semiconductor design.

The IEEE 1801 standard, also known as UPF (Unified Power Format), was developed by the IEEE to address the intricate challenges associated with power management in contemporary semiconductor designs. This standard offers a uniform framework for defining power domains, power states, and power intent, ensuring consistency across diverse tools and phases of the design process. By utilizing UPF, you can precisely model and regulate power consumption, a critical aspect for battery-operated devices, high-performance computing, and energy-efficient designs.

The key concepts of IEEE 1801 are:

1. Power domains
2. Power states
3. Power gating and isolation
4. Power switches
5. Level shifters, isolation, and retention cells
6. Macro model

Based on these building blocks, you write the power intent of the design.

The power intent for the design includes identifying/implementing low-power strategies that provide a clear description of the power architecture of a design.

The power definitions can effectively manage power consumption and ensure the chip meets its power and performance requirements.

You can start by creating the Power Supply Network, which defines how power is supplied to the design's various power domains and logic cells.

What's the next step to build the file? How do you understand the various concepts related to IEEE 1801? How do you complete the rest of the power intent file?

Relax!

Gear up to attend the training class created just for you to dive deep into the entire format and explore this exciting power specification method/format with hands-on labs in one day!

Training

Fundamentals of IEEE 1801 Low-Power Specification Format Training

This course is a complete tutorial for understanding the fundamentals of IEEE 1801 low-power specification format concepts. You learn about IEEE 1801 power supply networks, ground ports and nets, creating and connecting supply ports/nets, power domain, power switch, power states, defining isolation and level shifter strategies, hierarchical IEEE 1801, and various versions of the IEEE 1801. You also explore how power intent information can be used for a design across various flow stages, such as functional verification, synthesis, logic equivalency checking, place-and-route, test, timing signoff, power integrity, and so forth, using Cadence^® tools.

Labs

We ensure that your learning journey is smooth with hands-on labs covering various design scenarios.

Lab Videos

Now, the exciting part is that to help you further, we have created engaging videos of the training labs. You can refer to the lab module's instructions in demo format at https://support.cadence.com.

Lab Demo: Checking Power Supply Network in IEEE 1801 format and Running IEEE 1801 Quality Checks using Conformal Low Power

Lab Demo: Checking Power Intent for The Macro Connections in IEEE 1801 Format And Running IEEE 1801 Quality Checks using Conformal Low Power 

Online Class

Here is the course link.

Get ready for the most thrilling experience with Accelerated Learning!

The more you know, the faster you go!

Grab the cycle  or hike it, based on your existing knowledge.

Take the quiz and increase your learning pace!!

What's Next?

Grab your Badge after finishing the training and flaunt the expertise you have built up. 😊

Ready to take a tour of this power specification world? Let's help you enroll in this course.

We organize this training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information. If you want to ensure you are always the first to know about anything new in training, you can use the SUBSCRIBE button on the landing page to sign up for our regular training newsletters.

Related Short Training Bytes/Videos

Enhance the learning experience with short videos:

Genus Synthesis Solution: Video Library

 Joules RTL Power Solution: Video Library

Related Training

 Low-Power Synthesis Flow with Genus Synthesis Solution

Genus Low-Power Synthesis Flow with IEEE 1801

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Power Is HOT and Touches Everything and Everybody! But the Challenge Is To Deal With Low Power During Design Synthesis; How? - Digital Design - Cadence Blogs - Cadence Community

Binge on Chip Design Concepts this Weekend! - Digital Design - Cadence Blogs - Cadence Community

Conformal ECO Designer enables you to implement RTL engineering change orders (ECOs) for pre- and post-mask layout and offers early ECO prototyping capabilities for driving critical project decisions.

Conformal ECO compares two designs and generates a functional patch that implements the changes between the two designs.

One major criterion for determining patch quality is whether the patch can meet timing closure. To determine this, you typically need to run the time-consuming process of incremental synthesis and place-and-route. Instead, Conformal can analyze path logic depth changes before and after ECO patch generation. This provides a faster way to evaluate timing impact in patch generation stages.

After the patch is created and applied, it is passed to Genus to optimize the patch.

During patch optimization, you can choose to do many things like:

• Keeping constants in the patch
• Allowing tie cell inversion
• Specifying tie cell types
• Preserve DFF cells and cell types in the patch
• Preserve all cells and nets in the patch
• Preserve clock buffer cell in the patch
• Turn on/off sequential constant and sequential merge in patch optimization
• Allowing phase mapping for DFFs
• Map to spare cells
• Force fix DRC before timing

What's Next?

Join the Conformal ECO course to:

• Explore the many options and capabilities of Conformal ECO
• Use Conformal Engineering Change Order (ECO) for flat and hierarchical designs
• Generate a functional ECO patch, apply it to a design, optimize it, and map it to a specified technology
• Run a hierarchical design through ECO and run a comparison to prove the ECO is equivalent
• Run a postmask ECO using Conformal ECO GXL

Make sure you have experience with Conformal Equivalence Checker or completed the Conformal Equivalence Checking course before taking this course.

The online class is free for all Cadence customers with a Cadence Learning and Support Portal account. If you don’t have a Cadence Support account, go to Registration Help or Register Now and complete the requested information. For instructor-led training sessions "Live" or "Blended" please contact Cadence Training.

Please don't forget to obtain your Digital Badge after completing the training. Add your free digital badge to your email signature or any social media and networking platform to show your qualities and build trust, making you and your projects even more successful.

The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, machine learning-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and Cadence Cerebrus will intelligently optimize the Cadence digital full flow to meet the power, performance, and area (PPA) goals in a completely automated way. Use Cerebrus Apps to optimize some aspects of the design as well.

Running a full RTL to GDSII flow, Cadence Cerebrus has a lot of possibilities and combinations of different tool settings to explore.

Using the knowledge from previous runs, combined with on-the-fly analysis within the flow, Cadence Cerebrus can assess many settings combinations and fine-tune the flow accordingly in a very efficient manner.

As technology advances, projects become bigger and way more complex than before. The ability of a single engineer to run simultaneously a large number of blocks in a traditional way is limited. Cadence Cerebrus allows a single engineer to work more efficiently and implement more blocks, while maintaining the same or even better PPA, using compute power.

Being such a revolutionary tool, integrating Cerebrus into your existing flow is surprisingly simple as it can wrap around any existing flow scripts.

Please join me in this course, to learn about the features and basics of Cadence Cerebrus Intelligent Chip Explorer.

We’ll walk through the tool setting stage, explain what is a primitive and how it effects our run, talk about the cost function and the run goals.

We’ll understand the concept of scenarios, learn how to analyze the results of the different runs, and compare them.

In addition, we’ll talk about basic debug rules and methods to analyze failures.

Sounds Interesting?

Please join our “live” one-day Cadence Cerebrus Intelligent Chip Explorer Training @Cadence Feldkirchen planned for October 9th, 2024!

For more details and registration, please contact Training Germany.

If you would like to have an instructor-led training session in another region please contact your local training department.

Become Cadence Certified

Cadence Training Services offers a digital badge for this training course. This badge indicates proficiency in a certain technology or skill and gives you a way to validate your expertise to managers and potential employers. You can highlight your expertise by adding this digital badge to your email signature or any social media platform, such as Facebook or LinkedIn.

Related Training

Innovus Block Implementation with Stylus Common UI

Related Training Bytes

Cerebrus Primitives (Video) 

How to Reuse Cerebrus (Video) 

Cerebrus - Verifying Distribution Script (Video)

How to distribute Cerebrus Scenarios (Video) 

Cerebrus Web Interface Monitor and Control (Video) 

How to Setup Cerebrus for a Successful Run (Video) 

Flow Wrapping: The Cadence Cerebrus Intelligent Chip Explorer Must Have (Webinar) (Video) 

Cerebrus Cost Functions (Video) 

Related Blogs

Training Insights: Cadence Cerebrus Webinar Recording Now Available!

Keep Up with the Revolution—Cadence Cerebrus Training

New to Equivalence Checking? Restart from the Basic Concepts

Training Insights - Free Online Courses on Cadence Learning and Support Portal

Training Insights – Important Facts You Should know About Our Cadence Learning and Support Portal

In an era of abundant and constantly evolving information, the challenge is not just accessing knowledge but understanding and applying it effectively. AI is a transformative technology that is reshaping how we learn, work, and grow. In this blog, we’ll explore how AI accelerates our knowledge acquisition and understand how it can relate to the process of learning, which connects with our daily lives.

The role of AI is to accelerate knowledge by personalizing learning experiences, providing instant access to information, and offering data-driven insights. AI empowers us to learn more efficiently and effectively in many ways. I won't go into much detail, as we are already busy searching for the meaning of AI and what it can do; however, I want to share one inspiring fact about AI. It can analyze vast amounts of data in seconds, making sense of complex information and providing instantaneous actionable insights or concise answers. I understand that humans are looking to speed up things, which can help us understand technology better and perform our tasks faster.

The main reason AI is in focus is because of its ability to perform tasks faster than ever. We aim to enhance the performance of all our products, including the everyday household electronic items we use. Similarly, are we striving to accelerate the learning process? I am committed to assisting you, and one such method is concise, short (minute-long) videos.

In today's fast-paced world, where attention spans are shorter than ever, the rise of social media platforms has made it easier for anyone to create and share short videos. This is where minute videos come in. These bite-sized clips offer a quick and engaging way to deliver information to the audience with a significant impact. Understanding the definitions of technical terms in VLSI Design can often be accomplished in just a minute.

Below are the definitions of the essential stages in the RTL2GDSII Flow. For further reference, these definitions are also accessible on YouTube.

What is RTL Coding in VLSI Design?
What is Digital Verification?
What Is Synthesis in VLSI Design?
What Is Logic Equivalence Checking in VLSI Design?
What Is DFT in VLSI Design?
What is Digital Implementation?
What is Power Planning?
What are DRC and LVS in Physical Verification?
What are On-Chip Variations?

Want to Learn More?

The Cadence RTL-to-GDSII Flow training is available as both"Blended" and"Live" Please reach out to Cadence Training for further information.

And don't forget to obtain your Digital Badge after completing the training!

• You can check out a free Online Version of the training above, which is available 24/7 for all customers with a Cadence Learning ans Support Portal
• You will also have access to our Training Byte Library then which is full of hundres of troubleshooting videos, like the following: What is Digital Implementation?
• You can find more instructions how to get the best out of the Portal in this blog.
• If you would like to stay up-to-date with the latest news and information about Cadence trainings and webinars, subscribe to the Cadence Training emails.

Related Blogs

Training Insights – Why Is RTL Translated into Gate-Level Netlist?

Did You Miss the RTL-to-GDSII Webinar? No Worries, the Recording Is Available!

It’s the Digital Era; Why Not Showcase Your Brand Through a Digital Badge!

Binge on Chip Design Concepts this Weekend!

In this recent Training Webinar, we explore the concepts of RTL design, design verification, and coverage analysis while unveiling the exciting world of front-end design flow by guiding you through essential steps involved in creating integrated circuits—the building blocks of modern electronics.

We’ll break down the process into manageable stages, from defining the chip’s functionality to its physical realization. We’ll investigate the front-end part of the RTL-to-GDSII flow—from specification to functional verification and design coverage—and explore:

• Key concepts of specifying chip behavior and performance
• How to translate ideas into a digital blueprint and transform that into a design
• How to ensure your design is free of errors

Watch the Training Webinar recording from September 18, 2024: A Beginner’s Guide to RTL-to-GDSII Front-End Flow

Want to Learn More?

This link gives you more information about this RTL-to-GDSII Flow, the related training course, and a link to enroll:

Cadence RTL-to-GDSII Flow Training

The course includes slides with audio and downloadable laboratory exercises designed to emphasize the topics covered in the lecture. There is also a Digital Badge available for the training.

 Also, take this opportunity to register for the free Online Training related to this Webinar Topic.

Cadence RTL-to-GDSII Flow

Xcelium Simulator

Verilog Language and Application

Learning Maps

The online class is free for all Cadence customers with a Cadence Learning and Support Portal account. For instructor-led training sessions "Live" or "Blended" please contact Cadence Training.

Related Training Bytes

What is RTL Coding In VLSI Design?

What is Digital Verification?

What Is Synthesis in VLSI Design?

What Is Logic Equivalence Checking in VLSI Design?

What Is DFT in VLSI Design?

What is Digital Implementation?

What is Power Planning?

What are DRC and LVS in Physical Verification?

What are On-Chip Variations?

Related Blogs

Did You Miss the RTL-to-GDSII Webinar? No Worries, the Recording Is Available!

Training Insights – Why Is RTL Translated into Gate-Level Netlist?

Training Bytes: They May Be Shorter, But the Impact Is Stronger!

Cadence Support - A Round-the-Clock Problem Solver, Webinar Recording Available!

In the era of Artificial Intelligence, front-end designers need a magical key to empower them with technology that enables fully optimized RTL for implementation handoff and provides RTL designers with capabilities to accurately assist in the implementation convergence process.

The magic lies with Cadence Joules RTL Design Studio, an expert system that leverages generative AI for RTL design exploration, triages possible causes of violations, and additional insights that empower designers to understand how to address issues in their RTL, leading to smarter and more efficient chip design.

This unlocks the immense debugging and design analysis capabilities from a single, unified cockpit, enabling fully optimized RTL design prior to implementation handoff for the front-end designers and addresses all aspects of physical design by adding visibility into power, performance, area, and congestion (PPAC)

One critical component is the clock tree, which distributes the clock signal to all sequential elements, such as flip-flops and latches. Designers need the right techniques in the beginning stage to optimize the clock tree structure, ensuring that their designs meet the required timing specifications, reduce power consumption, maintain signal integrity, and increase reliability.

 This incredible feature is part of the Joules RTL Design Studio.

How do you efficiently explore the clock tree structure to optimize the results using Joules RTL Design Studio?

Joules Studio allows viewing a simplified version of the clock structure. This feature is primarily designed to help display clock frequency scaling through clock dividers. You can customize colors, symbols, and design elements using an input file. Additionally, you can cross-probe the custom clock tree structure to other widgets and the main schematic view in Joules Studio.

Moreover, with the clock tree preference features of the ideal clock tree wizard in Joules Studio GUI, you can highlight clock path, generate clocks and master clock, set case analysis, fold and unfold instances, undo and redo, set sense and disable timing, color preference, etc.

You can binge on these features through the channel videos posted on the support portal, which covers the Joules RTL Design Studio GUI Clock Tree Structure and Features of Ideal Clock Tree Wizard.

You can refer to the videos on Cadence Online Support(Cadence login required).

​Video Links:
Viewing Custom Clock Tree Structure in Joules RTL Design Studio (Video) 

Exploring Clock Tree Preference Widget of Ideal Clock Tree Wizard in Joules RTL Design Studio (Video) 

Want to learn more?

Explore the one-stop solutionJoules RTL Design Studio Product Page on Cadence Online Support(Cadence login required).

Related Resources 

Related Training Bytes:

Understanding Prototype Design Flow in Joules RTL Design Studio (Video)

Running Prototype Implementation Flow in Joules RTL Design Studio (Video)

Understanding Analyze Timing By Hierarchy In Joules RTL Design Studio (Video)

Related Courses:

• Joules Power Calculator

Want to Enroll in this Course?

We organize this training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information.

Please don't forget to obtain your Digital Badge after completing the training.

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Joules RTL Design Studio: Accelerating Fully Optimized RTL - Digital Design - Cadence Blogs - Cadence Community

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Is Design Power Estimation Lowering Your Power? Delegate and Relax! - Digital Design - Cadence Blogs - Cadence Community

The holiday week is here, and while this is a time for relaxing and re-energizing, it's also a perfect opportunity to continue learning and growing. Whether you're a student looking to stay ahead of the curve or a working professional with a thirst for new knowledge, our customer educational training bytes and online courses provide a fun, flexible way to learn during this holiday season.

What Content Is Available in the Digital Design and Signoff Domain?

If you want to explore/understand the complete flow quickly in two days, the Cadence RTL-to-GDSII flow course is for you. To understand how the RTL is synthesized into the gate-level netlist, explore the Genus Synthesis Solution with Stylus Common UI. 

To learn the detailed implementation flow, from floorplanning to routing, look into this course, Innovus Block Implementation with Stylus Common UI.

Interested in debugging and fixing timing violations with complete signoff techniques? Here is a detailed training course: Tempus Signoff Timing Analysis and Closure with Stylus Common UI. Are we sure the complete design works fine after manufacture? How do we keep the design ready for testing? Here are all the fundamentals: Design for Test Fundamentals Training.

How can logic be ensured at every stage of the flow? Can we compare the netlist at each stage? This step is popularly called logic equivalence checking and is related to the course Conformal Equivalence Checking Training.

I have highlighted only a few online courses in this blog, but for more courses on digital design topics, you can look into the learning maps with multiple online courses for each product to get a hands-on experience with labs.

Training Byte References

• How to Route a Design and Perform RC Extraction and Timing Analysis in Innovus Implementation System?
• How to Run Placement Optimization in the Innovus Implementation System?
• How to Run the Synthesis Without DFT?
• How to Run the Synthesis Flow with DFT?
• Creating Power Rings, Power Stripes, and Power Rails in the Innovus Implementation System
• How to Run Power Analysis and Analyze the Results in Innovus Implementation System?
• What are On-Chip Variations?
• What is RTL Coding In VLSI Design?
• What is Digital Verification?
• What Is Synthesis in VLSI Design?
• What Is Logic Equivalence Checking in VLSI Design?
• What Is DFT in VLSI Design?
• What is Digital Implementation?
• What is Power Planning?
• What are DRC and LVS in Physical Verification?

And don't forget, you can also obtain your Digital Badge after completing many of our training courses.

Becoming Cadence certified with a digital badge puts you ahead by making sure your skills get noticed.

It can help you win new opportunities with customers by showing your qualities and building trust, making you and your projects even more successful. All customers with a valid Cadence Learning and Support account can access the training online 24/7 for free.

If you don’t have a Cadence Support account yet, go to Cadence User Registration and complete the requested information. You can reach out to us at Cadence Training for information on courses, schedules, online training, or live on-site training.

Happy learning!

 With another year gone, we look back at our most popular blogs from the year and provide a summary of everything else that occurred in the education sector.

In 2024, we published 28more training blogs around Digital Design and Signoff and  proudly presented 1new webinar, if you missed it you can find the recording and  all future webinars we have  planned here.

Some of Our Most Viewed Blogs

Many thanks to all the coworkers who consistently updated their blogs with the most recent, fascinating Training Bytes and training materials. These are links to a few of the most popular blogs.

It’s the Digital Era; Why Not Showcase Your Brand Through a Digital Badge!

Training Insight – Dive into ATPG Flow with Cadence Modus DFT Software Solution 

Did You Miss the RTL-to-GDSII Webinar? No Worries, the Recording Is Available!          

Training Bytes: They May Be Shorter, But the Impact Is Stronger!    

New Training (s) Released in 2024

Genus Physical Synthesis Flow Training

Some of the Most Viewed Training Bytes in Blogs

How to use the Clock Tree Debugger in the Innovus Software

How to Run the Synthesis Without DFT? 

Steps for Multi-Mode Multi-Corner (MMMC) Flow in Genus Synthesis Solution

NewDigital Badges (some examples)

You can also get further information in this blog.

The Training Bytes blog series helped promote some of our Training Bytes, webinars, and scheduled dates for our "Blended" and "Live" trainings. The series also popularized our digital badges. For further information about our trainings, see the Training page and get a complete overview of our  learning map.

We hope that our blog series  helped you address your tasks faster and with ease. If you have any suggestions or desired topics on which you want us to blog, do let us know! 

You can also reach out to us at Cadence Training for information on courses, schedules, online trainings, or live on-site trainings.

RAKs

Please also consider our Rapid Adoption Kits on ASK which are continually updated, here are some recently published RAKs: 

• Ideal Power Analysis: A methodology Methodology to Identify, Debug and Fix wasted Wasted Power & and Mmeasure Power Efficiency
• Joules: Joules RAK for Beginners (Legacy) -Joules RTL Power Solution
• Introduction to Innovus Implementation System 23.10 & Block Implementation Flow

Here is Some More Interesting News From 2024

We introduced our new online training option  accelerated learning, which will help you to learn Cadence technical content in the fastest, most effective way.

Before starting an accelerated online course, take a pre-quiz to assess current knowledge, skip familiar content, and achieve training goals quickly.

Please find further guidance and explanations in this blog. 

The accelerated learning option is currently available for the following Digital Design and Signoff online trainings.

• Fundamentals of IEEE 1801 Low-Power Specification Format Training

• Basic Static Timing Analysis Training

We are very proud that we have developed and released our Onboarding Curriculum, especially for new hires, so that they can quickly learn the tools and technologies that will make them productive. Read more in this blog.

• The course on Artificial Intelligence (AI)/Machine Learning (ML) Fundamentals, which more customers completed in 2024, shows that more customers are predicting AI is the future.

• Cadence Cerebrus tool flow has advanced ML features that can design chips with the best PPA. In 2024, a significant number of customers received badges in the Cadence Cerebrus course.

• Cerebrus tool flow has advanced ML features that are able to design chips with the best PPA.  More customers have obtained badges on Course on Cerebrus in 2024.

• All DSG tools are equipped with ML features to enhance efficiency and accelerate semiconductor production.

• All customers with a valid Cadence Learning and Support account can access the trainings online 24/7 for free.
  
  
•  Learn how to maximize your experience with the Cadence Learning and Support portal by reading these blogs:

Cadence Learning and Support: New Courses Section in Content Notification Email

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The ISO 26262 standard provides functional safety guidance for semiconductors used in the automotive industry based on the foundational IEC 61508 standard. The Cadence Midas Safety Platform exchanges safety-related information across Cadence tools for a detailed safety analysis and generates a configuration database for your design. The semiconductor vendor does the safety analysis of the fully featured SoC and creates a Midas Safety RC database.

You can use this SoC and embedded software for your application with a modified safety scope, reconfigure the device safety mechanisms, or even add new safety mechanisms. With a vendor-enabled database, you can reassess the safety metrics and create the safety documentation for the reconfigured part.

Check out this video to learn more: Midas Safety Report Creator Introduction

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Related Courses

• Midas Safety Platform Introduction
• Functional Safety Implementation and Verification with Midas

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• Creating Architectural FMEDA in Midas
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With highly advanced technology, the real designs are getting complex, making the design optimization process complicated and comprising the design results. The sequential cells play a vital role in the chip's optimization and functioning.

Constant, merged, and unused flops, among other factors, impact the chip design's power, performance, and area (PPA) during the synthesis stage. Is there any way to handle the flops optimization for the best PPA results?

The solution lies with the Cadence Genus Synthesis Solution. The ultimate goal of the Genus Synthesis Solution is very simple: deliver the best possible productivity and Power, Performance, and Area (PPA) during register-transfer-level (RTL) logic synthesis of the chip.

 How do you manage the flop optimization?

• Unused registers on selected modules
• Disabling sequential merging
• Optimizing constants on specific flops
• Preventing register deletion
• Preventing Selective registers during elaboration
• Preventing merging of specific flops

Do you want to know how Genus Synthesis Solution manages all these? Explore the videos that cover how to control or enable/disable the optimization of registers or sequential elements in Genus. You can refer to the videos on the ASK Portal (Cadence login required).

Video Links

Removing Unused Registers on Selected Modules in Genus Synthesis Solution (Video)

Preventing Register Deletion in Genus Synthesis Solution (Video)

Disabling Sequential Merging in Genus Synthesis Solution (Video)

Preventing Merging of Specific Flops in Genus Synthesis Solution (Video)

Preserving Selective Registers During Elaboration in Genus Synthesis Solution (Video)

Optimizing Constants On Specific Flops in Genus Synthesis Solution (Video)

Related Resources 

​ Video Links: Enhance your knowledge of Genus and Joules with short videos

• Genus Synthesis Solution: Video Library
• Joules RTL Power Solution: Video Library

Want to Learn More?

Explore the one-stop solution product pages on the Application Support and Knowledge Portal (Cadence login required).

• Genus Synthesis Solution
• Joules RTL Power Solution

Related Courses

• Genus Synthesis Solution with Stylus Common UI
• Advanced Synthesis with Genus Stylus Common UI
• Low-Power Synthesis with Genus Stylus Common UI
• Genus Low-Power Synthesis Flow with IEEE1801
• Test Synthesis with Genus Stylus Common UI
• Joules Power Calculator
• Fundamentals of IEEE1801 Low-Power Specification Format

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