The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, machine learning-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and Cadence Cerebrus will intelligently optimize the Cadence digital full flow to meet the power, performance, and area (PPA) goals in a completely automated way. Use Cerebrus Apps to optimize some aspects of the design as well.

Running a full RTL to GDSII flow, Cadence Cerebrus has a lot of possibilities and combinations of different tool settings to explore.

Using the knowledge from previous runs, combined with on-the-fly analysis within the flow, Cadence Cerebrus can assess many settings combinations and fine-tune the flow accordingly in a very efficient manner.

As technology advances, projects become bigger and way more complex than before. The ability of a single engineer to run simultaneously a large number of blocks in a traditional way is limited. Cadence Cerebrus allows a single engineer to work more efficiently and implement more blocks, while maintaining the same or even better PPA, using compute power.

Being such a revolutionary tool, integrating Cerebrus into your existing flow is surprisingly simple as it can wrap around any existing flow scripts.

Please join me in this course, to learn about the features and basics of Cadence Cerebrus Intelligent Chip Explorer.

We’ll walk through the tool setting stage, explain what is a primitive and how it effects our run, talk about the cost function and the run goals.

We’ll understand the concept of scenarios, learn how to analyze the results of the different runs, and compare them.

In addition, we’ll talk about basic debug rules and methods to analyze failures.

Sounds Interesting?

Please join our “live” one-day Cadence Cerebrus Intelligent Chip Explorer Training @Cadence Feldkirchen planned for October 9th, 2024!

For more details and registration, please contact Training Germany.

If you would like to have an instructor-led training session in another region please contact your local training department.

Become Cadence Certified

Cadence Training Services offers a digital badge for this training course. This badge indicates proficiency in a certain technology or skill and gives you a way to validate your expertise to managers and potential employers. You can highlight your expertise by adding this digital badge to your email signature or any social media platform, such as Facebook or LinkedIn.

Related Training

Innovus Block Implementation with Stylus Common UI

Related Training Bytes

Cerebrus Primitives (Video) 

How to Reuse Cerebrus (Video) 

Cerebrus - Verifying Distribution Script (Video)

How to distribute Cerebrus Scenarios (Video) 

Cerebrus Web Interface Monitor and Control (Video) 

How to Setup Cerebrus for a Successful Run (Video) 

Flow Wrapping: The Cadence Cerebrus Intelligent Chip Explorer Must Have (Webinar) (Video) 

Cerebrus Cost Functions (Video) 

Related Blogs

Training Insights: Cadence Cerebrus Webinar Recording Now Available!

Keep Up with the Revolution—Cadence Cerebrus Training

New to Equivalence Checking? Restart from the Basic Concepts

Training Insights - Free Online Courses on Cadence Learning and Support Portal

Training Insights – Important Facts You Should know About Our Cadence Learning and Support Portal

In an era of abundant and constantly evolving information, the challenge is not just accessing knowledge but understanding and applying it effectively. AI is a transformative technology that is reshaping how we learn, work, and grow. In this blog, we’ll explore how AI accelerates our knowledge acquisition and understand how it can relate to the process of learning, which connects with our daily lives.

The role of AI is to accelerate knowledge by personalizing learning experiences, providing instant access to information, and offering data-driven insights. AI empowers us to learn more efficiently and effectively in many ways. I won't go into much detail, as we are already busy searching for the meaning of AI and what it can do; however, I want to share one inspiring fact about AI. It can analyze vast amounts of data in seconds, making sense of complex information and providing instantaneous actionable insights or concise answers. I understand that humans are looking to speed up things, which can help us understand technology better and perform our tasks faster.

The main reason AI is in focus is because of its ability to perform tasks faster than ever. We aim to enhance the performance of all our products, including the everyday household electronic items we use. Similarly, are we striving to accelerate the learning process? I am committed to assisting you, and one such method is concise, short (minute-long) videos.

In today's fast-paced world, where attention spans are shorter than ever, the rise of social media platforms has made it easier for anyone to create and share short videos. This is where minute videos come in. These bite-sized clips offer a quick and engaging way to deliver information to the audience with a significant impact. Understanding the definitions of technical terms in VLSI Design can often be accomplished in just a minute.

Below are the definitions of the essential stages in the RTL2GDSII Flow. For further reference, these definitions are also accessible on YouTube.

What is RTL Coding in VLSI Design?
What is Digital Verification?
What Is Synthesis in VLSI Design?
What Is Logic Equivalence Checking in VLSI Design?
What Is DFT in VLSI Design?
What is Digital Implementation?
What is Power Planning?
What are DRC and LVS in Physical Verification?
What are On-Chip Variations?

Want to Learn More?

The Cadence RTL-to-GDSII Flow training is available as both"Blended" and"Live" Please reach out to Cadence Training for further information.

And don't forget to obtain your Digital Badge after completing the training!

• You can check out a free Online Version of the training above, which is available 24/7 for all customers with a Cadence Learning ans Support Portal
• You will also have access to our Training Byte Library then which is full of hundres of troubleshooting videos, like the following: What is Digital Implementation?
• You can find more instructions how to get the best out of the Portal in this blog.
• If you would like to stay up-to-date with the latest news and information about Cadence trainings and webinars, subscribe to the Cadence Training emails.

Related Blogs

Training Insights – Why Is RTL Translated into Gate-Level Netlist?

Did You Miss the RTL-to-GDSII Webinar? No Worries, the Recording Is Available!

It’s the Digital Era; Why Not Showcase Your Brand Through a Digital Badge!

Binge on Chip Design Concepts this Weekend!

In this recent Training Webinar, we explore the concepts of RTL design, design verification, and coverage analysis while unveiling the exciting world of front-end design flow by guiding you through essential steps involved in creating integrated circuits—the building blocks of modern electronics.

We’ll break down the process into manageable stages, from defining the chip’s functionality to its physical realization. We’ll investigate the front-end part of the RTL-to-GDSII flow—from specification to functional verification and design coverage—and explore:

• Key concepts of specifying chip behavior and performance
• How to translate ideas into a digital blueprint and transform that into a design
• How to ensure your design is free of errors

Watch the Training Webinar recording from September 18, 2024: A Beginner’s Guide to RTL-to-GDSII Front-End Flow

Want to Learn More?

This link gives you more information about this RTL-to-GDSII Flow, the related training course, and a link to enroll:

Cadence RTL-to-GDSII Flow Training

The course includes slides with audio and downloadable laboratory exercises designed to emphasize the topics covered in the lecture. There is also a Digital Badge available for the training.

 Also, take this opportunity to register for the free Online Training related to this Webinar Topic.

Cadence RTL-to-GDSII Flow

Xcelium Simulator

Verilog Language and Application

Learning Maps

The online class is free for all Cadence customers with a Cadence Learning and Support Portal account. For instructor-led training sessions "Live" or "Blended" please contact Cadence Training.

Related Training Bytes

What is RTL Coding In VLSI Design?

What is Digital Verification?

What Is Synthesis in VLSI Design?

What Is Logic Equivalence Checking in VLSI Design?

What Is DFT in VLSI Design?

What is Digital Implementation?

What is Power Planning?

What are DRC and LVS in Physical Verification?

What are On-Chip Variations?

Related Blogs

Did You Miss the RTL-to-GDSII Webinar? No Worries, the Recording Is Available!

Training Insights – Why Is RTL Translated into Gate-Level Netlist?

Training Bytes: They May Be Shorter, But the Impact Is Stronger!

Cadence Support - A Round-the-Clock Problem Solver, Webinar Recording Available!

In the era of Artificial Intelligence, front-end designers need a magical key to empower them with technology that enables fully optimized RTL for implementation handoff and provides RTL designers with capabilities to accurately assist in the implementation convergence process.

The magic lies with Cadence Joules RTL Design Studio, an expert system that leverages generative AI for RTL design exploration, triages possible causes of violations, and additional insights that empower designers to understand how to address issues in their RTL, leading to smarter and more efficient chip design.

This unlocks the immense debugging and design analysis capabilities from a single, unified cockpit, enabling fully optimized RTL design prior to implementation handoff for the front-end designers and addresses all aspects of physical design by adding visibility into power, performance, area, and congestion (PPAC)

One critical component is the clock tree, which distributes the clock signal to all sequential elements, such as flip-flops and latches. Designers need the right techniques in the beginning stage to optimize the clock tree structure, ensuring that their designs meet the required timing specifications, reduce power consumption, maintain signal integrity, and increase reliability.

 This incredible feature is part of the Joules RTL Design Studio.

How do you efficiently explore the clock tree structure to optimize the results using Joules RTL Design Studio?

Joules Studio allows viewing a simplified version of the clock structure. This feature is primarily designed to help display clock frequency scaling through clock dividers. You can customize colors, symbols, and design elements using an input file. Additionally, you can cross-probe the custom clock tree structure to other widgets and the main schematic view in Joules Studio.

Moreover, with the clock tree preference features of the ideal clock tree wizard in Joules Studio GUI, you can highlight clock path, generate clocks and master clock, set case analysis, fold and unfold instances, undo and redo, set sense and disable timing, color preference, etc.

You can binge on these features through the channel videos posted on the support portal, which covers the Joules RTL Design Studio GUI Clock Tree Structure and Features of Ideal Clock Tree Wizard.

You can refer to the videos on Cadence Online Support(Cadence login required).

​Video Links:
Viewing Custom Clock Tree Structure in Joules RTL Design Studio (Video) 

Exploring Clock Tree Preference Widget of Ideal Clock Tree Wizard in Joules RTL Design Studio (Video) 

Want to learn more?

Explore the one-stop solutionJoules RTL Design Studio Product Page on Cadence Online Support(Cadence login required).

Related Resources 

Related Training Bytes:

Understanding Prototype Design Flow in Joules RTL Design Studio (Video)

Running Prototype Implementation Flow in Joules RTL Design Studio (Video)

Understanding Analyze Timing By Hierarchy In Joules RTL Design Studio (Video)

Related Courses:

• Joules Power Calculator

Want to Enroll in this Course?

We organize this training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information.

Please don't forget to obtain your Digital Badge after completing the training.

Related Blogs:

Let's Discover the Secret to Enhance Design's PPAC in a Single Cockpit! - Digital Design - Cadence Blogs - Cadence Community

Joules RTL Design Studio: Accelerating Fully Optimized RTL - Digital Design - Cadence Blogs - Cadence Community

Let's Replay the Process of Power Estimation with the Power of 'x'! - Digital Design - Cadence Blogs - Cadence Community

Is Design Power Estimation Lowering Your Power? Delegate and Relax! - Digital Design - Cadence Blogs - Cadence Community

The holiday week is here, and while this is a time for relaxing and re-energizing, it's also a perfect opportunity to continue learning and growing. Whether you're a student looking to stay ahead of the curve or a working professional with a thirst for new knowledge, our customer educational training bytes and online courses provide a fun, flexible way to learn during this holiday season.

What Content Is Available in the Digital Design and Signoff Domain?

If you want to explore/understand the complete flow quickly in two days, the Cadence RTL-to-GDSII flow course is for you. To understand how the RTL is synthesized into the gate-level netlist, explore the Genus Synthesis Solution with Stylus Common UI. 

To learn the detailed implementation flow, from floorplanning to routing, look into this course, Innovus Block Implementation with Stylus Common UI.

Interested in debugging and fixing timing violations with complete signoff techniques? Here is a detailed training course: Tempus Signoff Timing Analysis and Closure with Stylus Common UI. Are we sure the complete design works fine after manufacture? How do we keep the design ready for testing? Here are all the fundamentals: Design for Test Fundamentals Training.

How can logic be ensured at every stage of the flow? Can we compare the netlist at each stage? This step is popularly called logic equivalence checking and is related to the course Conformal Equivalence Checking Training.

I have highlighted only a few online courses in this blog, but for more courses on digital design topics, you can look into the learning maps with multiple online courses for each product to get a hands-on experience with labs.

Training Byte References

• How to Route a Design and Perform RC Extraction and Timing Analysis in Innovus Implementation System?
• How to Run Placement Optimization in the Innovus Implementation System?
• How to Run the Synthesis Without DFT?
• How to Run the Synthesis Flow with DFT?
• Creating Power Rings, Power Stripes, and Power Rails in the Innovus Implementation System
• How to Run Power Analysis and Analyze the Results in Innovus Implementation System?
• What are On-Chip Variations?
• What is RTL Coding In VLSI Design?
• What is Digital Verification?
• What Is Synthesis in VLSI Design?
• What Is Logic Equivalence Checking in VLSI Design?
• What Is DFT in VLSI Design?
• What is Digital Implementation?
• What is Power Planning?
• What are DRC and LVS in Physical Verification?

And don't forget, you can also obtain your Digital Badge after completing many of our training courses.

Becoming Cadence certified with a digital badge puts you ahead by making sure your skills get noticed.

It can help you win new opportunities with customers by showing your qualities and building trust, making you and your projects even more successful. All customers with a valid Cadence Learning and Support account can access the training online 24/7 for free.

If you don’t have a Cadence Support account yet, go to Cadence User Registration and complete the requested information. You can reach out to us at Cadence Training for information on courses, schedules, online training, or live on-site training.

Happy learning!

 With another year gone, we look back at our most popular blogs from the year and provide a summary of everything else that occurred in the education sector.

In 2024, we published 28more training blogs around Digital Design and Signoff and  proudly presented 1new webinar, if you missed it you can find the recording and  all future webinars we have  planned here.

Some of Our Most Viewed Blogs

Many thanks to all the coworkers who consistently updated their blogs with the most recent, fascinating Training Bytes and training materials. These are links to a few of the most popular blogs.

It’s the Digital Era; Why Not Showcase Your Brand Through a Digital Badge!

Training Insight – Dive into ATPG Flow with Cadence Modus DFT Software Solution 

Did You Miss the RTL-to-GDSII Webinar? No Worries, the Recording Is Available!          

Training Bytes: They May Be Shorter, But the Impact Is Stronger!    

New Training (s) Released in 2024

Genus Physical Synthesis Flow Training

Some of the Most Viewed Training Bytes in Blogs

How to use the Clock Tree Debugger in the Innovus Software

How to Run the Synthesis Without DFT? 

Steps for Multi-Mode Multi-Corner (MMMC) Flow in Genus Synthesis Solution

NewDigital Badges (some examples)

You can also get further information in this blog.

The Training Bytes blog series helped promote some of our Training Bytes, webinars, and scheduled dates for our "Blended" and "Live" trainings. The series also popularized our digital badges. For further information about our trainings, see the Training page and get a complete overview of our  learning map.

We hope that our blog series  helped you address your tasks faster and with ease. If you have any suggestions or desired topics on which you want us to blog, do let us know! 

You can also reach out to us at Cadence Training for information on courses, schedules, online trainings, or live on-site trainings.

RAKs

Please also consider our Rapid Adoption Kits on ASK which are continually updated, here are some recently published RAKs: 

• Ideal Power Analysis: A methodology Methodology to Identify, Debug and Fix wasted Wasted Power & and Mmeasure Power Efficiency
• Joules: Joules RAK for Beginners (Legacy) -Joules RTL Power Solution
• Introduction to Innovus Implementation System 23.10 & Block Implementation Flow

Here is Some More Interesting News From 2024

We introduced our new online training option  accelerated learning, which will help you to learn Cadence technical content in the fastest, most effective way.

Before starting an accelerated online course, take a pre-quiz to assess current knowledge, skip familiar content, and achieve training goals quickly.

Please find further guidance and explanations in this blog. 

The accelerated learning option is currently available for the following Digital Design and Signoff online trainings.

• Fundamentals of IEEE 1801 Low-Power Specification Format Training

• Basic Static Timing Analysis Training

We are very proud that we have developed and released our Onboarding Curriculum, especially for new hires, so that they can quickly learn the tools and technologies that will make them productive. Read more in this blog.

• The course on Artificial Intelligence (AI)/Machine Learning (ML) Fundamentals, which more customers completed in 2024, shows that more customers are predicting AI is the future.

• Cadence Cerebrus tool flow has advanced ML features that can design chips with the best PPA. In 2024, a significant number of customers received badges in the Cadence Cerebrus course.

• Cerebrus tool flow has advanced ML features that are able to design chips with the best PPA.  More customers have obtained badges on Course on Cerebrus in 2024.

• All DSG tools are equipped with ML features to enhance efficiency and accelerate semiconductor production.

• All customers with a valid Cadence Learning and Support account can access the trainings online 24/7 for free.
  
  
•  Learn how to maximize your experience with the Cadence Learning and Support portal by reading these blogs:

Cadence Learning and Support: New Courses Section in Content Notification Email

Cadence Learning and Support: Installation and Licensing Help via Chatbot

Please don´t forget to SUBSCRIBE to the Cadence Training Newsletter to receive updates about upcoming training, webinars, and much more. If you have any questions about courses, schedules, online training, blended/virtual live training, or public, or onsite live training, reach out to us at Cadence Training

to the Cadence training newsletter to be updated about upcoming training, webinars, and much more. If you have any questions about courses, schedules, online training, blended/virtual live training, or public, or onsite live training, reach out to us at Cadence Training.

Related Blogs

Training Insights: Cadence Certus Closure Solution Badge Now Available!

Training Insights Accelerated Learning – The more More you You knowKnow, the faster Faster Yyou goGo

If You Don't See It, You Might Miss It!

The ISO 26262 standard provides functional safety guidance for semiconductors used in the automotive industry based on the foundational IEC 61508 standard. The Cadence Midas Safety Platform exchanges safety-related information across Cadence tools for a detailed safety analysis and generates a configuration database for your design. The semiconductor vendor does the safety analysis of the fully featured SoC and creates a Midas Safety RC database.

You can use this SoC and embedded software for your application with a modified safety scope, reconfigure the device safety mechanisms, or even add new safety mechanisms. With a vendor-enabled database, you can reassess the safety metrics and create the safety documentation for the reconfigured part.

Check out this video to learn more: Midas Safety Report Creator Introduction

Want to share this and other great Cadence learning opportunities with someone else? Tell them to subscribe.

Hungry for training? Choose the Cadence Training Menu that’s right for you.

Related Courses

• Midas Safety Platform Introduction
• Functional Safety Implementation and Verification with Midas

Related Blogs

• All EVs Need the Midas Functional Safety Platform

Related Videos

• Creating Architectural FMEDA in Midas
• Creating Detailed FMEDA in Midas

Please see course learning maps for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.

*If you don’t have a Cadence Support account, go to Cadence User Registration and complete the requested information. Or visit Registration Help.

With highly advanced technology, the real designs are getting complex, making the design optimization process complicated and comprising the design results. The sequential cells play a vital role in the chip's optimization and functioning.

Constant, merged, and unused flops, among other factors, impact the chip design's power, performance, and area (PPA) during the synthesis stage. Is there any way to handle the flops optimization for the best PPA results?

The solution lies with the Cadence Genus Synthesis Solution. The ultimate goal of the Genus Synthesis Solution is very simple: deliver the best possible productivity and Power, Performance, and Area (PPA) during register-transfer-level (RTL) logic synthesis of the chip.

 How do you manage the flop optimization?

• Unused registers on selected modules
• Disabling sequential merging
• Optimizing constants on specific flops
• Preventing register deletion
• Preventing Selective registers during elaboration
• Preventing merging of specific flops

Do you want to know how Genus Synthesis Solution manages all these? Explore the videos that cover how to control or enable/disable the optimization of registers or sequential elements in Genus. You can refer to the videos on the ASK Portal (Cadence login required).

Video Links

Removing Unused Registers on Selected Modules in Genus Synthesis Solution (Video)

Preventing Register Deletion in Genus Synthesis Solution (Video)

Disabling Sequential Merging in Genus Synthesis Solution (Video)

Preventing Merging of Specific Flops in Genus Synthesis Solution (Video)

Preserving Selective Registers During Elaboration in Genus Synthesis Solution (Video)

Optimizing Constants On Specific Flops in Genus Synthesis Solution (Video)

Related Resources 

​ Video Links: Enhance your knowledge of Genus and Joules with short videos

• Genus Synthesis Solution: Video Library
• Joules RTL Power Solution: Video Library

Want to Learn More?

Explore the one-stop solution product pages on the Application Support and Knowledge Portal (Cadence login required).

• Genus Synthesis Solution
• Joules RTL Power Solution

Related Courses

• Genus Synthesis Solution with Stylus Common UI
• Advanced Synthesis with Genus Stylus Common UI
• Low-Power Synthesis with Genus Stylus Common UI
• Genus Low-Power Synthesis Flow with IEEE1801
• Test Synthesis with Genus Stylus Common UI
• Joules Power Calculator
• Fundamentals of IEEE1801 Low-Power Specification Format

Want to Enroll in this Course?

We've organized this training for you as "blended" or "Live" training. Please reach out to Cadence Training for further information.

If you want to ensure you are always the first to know about anything new in training, you can use the SUBSCRIBE button on the landing page to sign up for our regular training newsletters.

What's Next?

Grab your Digital Badge after finishing the training and flaunt what expertise you have built up. 😊

Please don't forget to obtain your Digital Badge after completing the training.

Related Blogs

It's the Digital Era; Why Not Showcase Your Brand Through a Digital Badge!

Training Insights – Struggling with Synthesis to Achieve Best PPA Results? - Digital Design - Cadence Blogs - Cadence Community

Unlocking the Concepts of IEEE 1801 Standard for Efficient Power Management - Digital Design - Cadence Blogs - Cadence Community

A Magical World - The Incredible Clock Tree Wizard to Augment Productivity and QoR! - Digital Design - Cadence Blogs - Cadence Community

Have you ever wondered how a predator succeeds (or) a prey escapes in the jungle? It’s the breathtaking speed and agility of the predator (say, a leopard) 🐆 as it chases prey (say, a deer)🦌.

The VLSI circuit operation is very similar. If the driving cell is strong, it takes less delay and changes the output quicker than a weaker driver, which produces a sluggish response and takes longer to produce the same effect at the output pin Q.

Before going into the details, let us know what these terms (cell delay and cell drive strength) mean and why should we take care?

Drive strength and cell delay are two key concepts in digital circuit design, particularly in standard cell libraries used for ASIC and FPGA design. They are closely related and impact timing, power, and area considerations in a design.

Cell Delay

Cell delay refers to the propagation delay of a logic cell, which is the time taken for a change at the input to reflect at the output. It is a function of the input transition time and the effective load at the output pin.

Drive Strength

Drive strength refers to the ability of a logic cell (such as an inverter, buffer, NAND, NOR, etc.) to drive a load. It is usually represented as multiples of a base drive (e.g., X1, X2, X4, X8, etc.), where higher drive strength (X32, X16, etc.) means the cell can provide more current and drive larger loads (longer interconnects, multiple fan-outs). Lower drive strength (X1, X2, etc.) means the cell is weaker and is suitable for driving small loads. As shown in the example below, BUFX2 has lower drive strength, and its delay is higher (high transition time ). BUFX16 has higher drive strength, and its delay is lesser (low transition time).

Relationship Between Drive Strength and Cell Delay

There is an inverse relationship between drive strength and cell delay:
a) Higher drive strength → Lower cell delay: A stronger cell can charge/discharge the output node faster, reducing delay.
b) Lower drive strength → Higher cell delay: A weaker cell takes longer to switch the output due to limited drive current.
However, increasing drive strength comes with trade-offs:
a) Increased area: Higher drive strength cells have larger transistors, which take up more silicon area.
b) Higher power consumption: Larger transistors have higher leakage and dynamic power consumption.

In the below example, you can notice that a higher drive strength cell(BUFX20) has less transition time (0.0349ns), results in less cell delay, and a lower drive strength cell (BUFX2) has a higher transition time (0.1063ns) that results in high cell delay. You can also understand how the area will be affected by different drive strength cells.                              

Choosing the Right Drive Strength

In timing optimization, drive strength selection is a key technique:
a) For high-speed paths, stronger drive strength cells are used to reduce delay.
b) For power-efficient design, weaker drive strength cells are used where speed is not critical.
c) Buffer insertion and sizing: Designers optimize timing by inserting buffers of appropriate drive strengths.

               
Practical Example

Consider a NAND gate with different drive strengths:
- A NAND2_X1 might have a cell delay of 50 ps when driving a small load.
- A NAND2_X8 might have a cell delay of 15 ps for the same load but will consume more power.

Thus, designers must balance drive strength and delay to meet timing constraints while minimizing power and area.

Would you like further details on a specific aspect, such as how EDA tools optimize drive strength?

This Cadence RTL-to- GDSII Flow training course contains the Timing Signoff module that demonstrates the impact of cell delay for different drive strengths for you. Please reach out to Cadence Training for further information.

The course includes slides with audio and downloadable laboratory exercises designed to emphasize the topics covered in the lecture. There is also a Digital Badge available for the training.

You can also access the lab demos created for each course module through a channel video RTL-to-GDSII lab demo videos.

If you want to learn in detail about the Timing Concepts, STA, and Timing Signoff, you can take the following two courses.

• Basic Static Timing Analysis— In this course, you can learn all the basics of STA.
• Tempus Signoff Timing Analysis and Closure with Stylus Common UI— In this course, you can learn the detailed flow of timing sign-off, with multiple techniques to analyze and resolve all the timing violations (including manual ECOs flow).

Also, the following short training bytes help you understand the concepts quickly, and a few demonstrate how to debug and resolve errors; for more, look here: Training Bytes (Videos)

Training Byte References

• Demo: How to Run Timing Analysis Using the Innovus Implementation System? (Video)
• Demo: How to Run an Independent Timing Analysis In Tempus? (Video)
• Demo: How to Rerun the Innovus to fix all timing violations in Tempus? (Video)
• Demo: How to Highlight the Timing path in Innovus Implementation System
• How to Run Placement Optimization in the Innovus Implementation System?
• How to Run the Synthesis Without DFT?
• How to Run the Synthesis Flow With DFT?
• Creating Power Rings, Power Stripes, and Power Rails in the Innovus Implementation System
• How to Run Power Analysis and Analyze the Results in Innovus Implementation System?
• What are On-Chip Variations?
• What is RTL Coding In VLSI Design?
• What is Digital Verification?
• What Is Synthesis in VLSI Design?
• What Is Logic Equivalence Checking in VLSI Design?
• What Is DFT in VLSI Design?
• What is Digital Implementation?
• What is Power Planning?
• What are DRC and LVS in Physical Verification?

Related Blogs

• Here Is the Recording of the RTL-to-GDSII Flow FrontEnd Webinar!
• Training Insights – Why Is RTL Translated into Gate-Level Netlist?
• Training Bytes: They May Be Shorter, But the Impact Is Stronger!

For more information on Cadence's digital design and signoff products and services, visit www.cadence.com.

If you want to receive periodic news and information about Cadence, please sign up and select the topics that interest you.

Happy learning! Thank You.

If you're a chip designer or verification engineer, you have likely spent countless hours stressing over whether your design block is functionally accurate; in other words, "Will my chip actually do what it's supposed to?" Today, Cadence is announcing the next evolutions of its Conformal family of products to help you answer that exact question better. Introducing: Conformal AI Studio. I want to take a few words to tell you what inspired the technology, how it works, and why you should care.

The Critical Role of LEC

Logical equivalence checking (LEC) is pivotal in the design implementation process. Traditionally, it allows designers to verify that the functionality remains consistent through various design stages without the need for extensive retesting. By testing the design once at the register transfer level (RTL) and then formally proving that subsequent stages—ranging from gate-level designs to final transistor implementations—are logically equivalent, it not only saves time but also reduces costs significantly. This methodology has long been the backbone of cost-effective verification strategies. However, the last 10 to 15 years have witnessed a paradigm shift in the complexity of designs and the corresponding challenges with LEC.

With SoCs containing 100 times more logic than in previous years and a substantial increase in the number of power domains and functional engineering change orders (ECOs), traditional methods of proving logical equivalence have become increasingly inadequate. The growth of advanced synthesis optimizations, which have proliferated from merely a handful of critical blocks to become a ubiquitous element of the design process, adds to this complexity. Despite these challenges, the fundamental technology underpinning LEC had only seen incremental improvements. As a result, a new approach toward verification is paramount, one that reconsiders the way equivalence is established.

Rethinking Equivalence: A Shift in Approach

To genuinely address the complexities in today's semiconductor designs, the industry must transition from the outdated methodology of proving designs as equivalent in isolation. Real-world designs are not static; they have a life cycle characterized by continuous growth and change. Each stage of a project generates a wealth of historical data that often goes untapped. I would claim that, through most of its history, EDA implementation by default has amnesia. This same inefficiency applies to solutions related to logical equivalence. Our industry must better leverage historical insights to inform and enhance current software solutions.

Embracing AI and ML

One of the most promising avenues for augmenting semiconductor design productivity lies in applying AI and ML techniques. EDA companies, with Cadence at the forefront, are actively deploying these advanced methodologies to streamline chip design and verification processes. AI-driven solutions can vastly improve efficiency by introducing predictive capabilities that draw on historical data. Moreover, AI can assist in optimizing synthesis results by recognizing which optimizations are likely to impact equivalence.

So, given the longstanding value of equivalence checking, the need for a shift in approach, and the broader EDA trends in artificial intelligence and machine learning (AI/ML), what exactly is Cadence announcing today with Conformal AI Studio?

Conformal AI Studio: Core Benefits

Conformal AI is a comprehensive suite that reimagines the current Conformal products and delivers three key new benefits:

• We're delivering critical productivity improvements that will make users an order of magnitude more efficient. This is possible due to simplified setup and core engine speedups, including a new distributed low-power engine that allows us to scale full chip power signoff to billions of instances. Our new AI-based diagnostic dashboards will streamline usage and enable cross-project insights, while ML-driven abort resolution will help solve one of the most complex problems our advanced users face today.
• We are introducing a new SmartECO flow that delivers up to 10X better runtime and patch size. We're leveraging earlier RTL-level information and new Boolean optimization algorithms to handle designs with many hierarchies and advanced datapath, while our AI-driven recipe selection makes implementing functional ECOs simple and efficient.
• While the Conformal family is committed to always being implementation tool agnostic, we're doubling down on ensuring our flows work best with our Cadence tools. New support for sequential optimizations in the Cadence Genus, Joules, and Innovus solutions, as well as expanded reinforcement learning techniques, can help both lower power and improve performance.

Conformal AI Studio: AI/ML Innovations

In addition to these critical new core engines and flow improvements, this generation of Conformal technology leverages AI/ML in a number of new ways. Deep integrations to Cadence's JedAI big data platform allow design teams to mine data across a project's history and learn from customers' unique design styles and tool strategies. Conformal AI Studio can now intelligently spawn off multiple parallel scenarios using the Cadence Cerebrus reinforcement learning system to rapidly explore the full solution spaces for the most challenging problems, like proving equivalence when facing complex aborts or ensuring ECO patches are both functionally optimal and implementable through place-and-route, STA, and physical signoff.

Conformal AI Studio: Always Implementation Agnostic

For decades, the Conformal family has been the industry leader in the LEC subset of formal verification and is the key auditor for ensuring that digital implementation tools from both Cadence and other EDA vendors do what they're supposed to. We have never wavered from that mission of being your trusted golden signoff regardless of your implementation flow, and the Cadence Conformal AI Studio represents the exciting next chapter.

Conformal AI Studio: New Product Offerings

Taken together, these Conformal AI Studio innovations will help your implementation teams achieve their design goals and are available from three core products:

• Conformal AI Equivalence– Enables distributed Boolean LEC, AI dashboards, and ML-driven proof engines
• Conformal AI ECO– Automates pre- and post-mask functional ECO generation, creating high-quality, efficient, and implementable patches that ensure schedule predictability
• Conformal AI Low Power– Verifies that low-power circuit structures in complex SoCs match the design's power intent using distributed and hierarchical flows and performs efficient two-design low-power compare

Conclusion

As the semiconductor industry grapples with soaring design complexities, harnessing innovative technologies becomes increasingly urgent. LEC remains a cornerstone of verification practices, but its evolution is necessary to meet contemporary challenges. By embracing the capabilities of AI and ML, we can help you turn data into actionable insights, optimize workflows, and foster collaboration across teams. This is not just about keeping pace; it's about leading the charge toward a future where engineers can design smarter, faster, and more efficiently than ever before. The transformation is underway, and Cadence can help chip designs confidently answer that overarching question of "Will my chip do what it's supposed to?" with "Yes, it will, when you sign off with Conformal AI Studio!"

Learn more about Conformal AI Studio.

Optimizing power can be a very convoluted and crucial process. To make design chips meet throughput goals and optimal power consumption, you need to plan right from the beginning! Power is HOT and touches everything and everybody!

Low-power synthesis is one of the important stages in the full IC flow. Using various techniques, you synthesize the design from behavioral description to gates while optimizing for dynamic and leakage power. Do you want to use multiple supply voltage (MSV) design, power shutoff (PSO) synthesis, dynamic voltage frequency scaling (DVFS), or other techniques to optimize your power results?

But stuck as you are new to the low-power world, do the various power terminologies look like a complicated maze for you?

1. Power domains
2. Power intent
3. Power modes
4. Level shifter
5. Isolation logic
6. State retention power gating
7. Gate-level dynamic power optimization
8. Clock gating
9. Multiple threshold voltage
10. Power shutoff
11. Dynamic voltage frequency scaling
12. Glitch

The list goes on…

Wondering how to enhance your knowledge of these concepts to ensure proper planning for low-power optimization? Gear up! You don't need too many resources to elevate your proficiency.

We believe disseminating the knowledge amplifies its power. We want you to leverage our vast resources to develop expertise and knowledge of various chip design concepts and flows. The magic lies in your pocket! Unlock your mobile and start relaxing with YouTube videos!

Er…don't get confused! The Cadence YouTube channel hosts a Customer Education Training Bytes channel. This provides a video repository of short conceptual videos on YouTube. The learning is just a click away! Click the links below to explore the basic low-power terminologies and more!

What Are Power Domains

What Is Power Intent

What are Power modes

What Is a Level Shifter

What Is an Isolation Logic

What Is State Retention Power Gating

How to do Gate Level Dynamic Power Optimization

How to Optimize Dynamic Power

What is Clock Gating and How to Reduce Clock Power

Understanding Multiple Threshold Voltage Optimization

What Are Multiple Supply Voltage and Power Shutoff Methodologies?

What Is Dynamic Voltage Frequency Scaling

What Is a Glitch

 As a next step, you can further leverage the vast database of videos and detailed training on Cadence Application Support and Knowledge Portal (Cadence login required).

Related Resources

Video Links: Enhance your knowledge of Genus and Joules with short videos

• Genus Synthesis Solution: Video Library
• Joules RTL Power Solution: Video Library

Want to Learn More?

Explore the one-stop solution product pages on Cadence Application Support and Knowledge Portal (Cadence login required).

• Genus Synthesis Solution
• Joules RTL Power Solution

Related Courses

• Advanced Synthesis with Genus Stylus Common UI

• Fundamentals of IEEE 1801 Low-Power Specification Format
• Genus Low-Power Synthesis Flow with IEEE 1801
• Genus Physical Synthesis Flow
• Genus Synthesis Solution with Stylus Common UI
• Joules Power Calculator
• Low-Power Synthesis Flow with Genus Stylus Common UI
• Test Synthesis with Genus Stylus Common UI

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Have you ever found yourself in an Italian restaurant, twirling your fork around a plate of delicious spaghetti? Good spaghetti is a true gift, but spaghetti code? Not so much.

Spaghetti code refers to complex, tangled programming code that is a nightmare to follow and maintain. We've all been there when we have inherited code from someone who has moved on, and it's now our job to maintain it or debug it in a crisis.

Just like a plate of spaghetti where every strand is intertwined, spaghetti code's intricacies can make a programmer's job unnecessarily complicated.

Here's why simple programming commands are preferred over complex ones and how embracing simplicity can save your sanity—and time.

Simple code is like a straight road—it efficiently gets you from point A to point B. It's easy to read, debug, and maintain. When you write simple code, you're doing yourself a favor and helping anyone who might have to deal with your code in the future. It's like leaving clear signposts for fellow travelers, ensuring that no one gets lost in a maze of convoluted instructions.

On the other hand, complex code is the equivalent of sending someone on a detour through a dense forest with a vague map. They might eventually find their way, but not without frustration and wasted time. Keeping your code simple ensures that the journey is smooth and straightforward.

A Simple TCL Example

Here's a basic example of a TCL script that reverses a string:

set str "Hello, World!"

set reversed_str [string reverse $str]

puts $reversed_str

This script uses the set command to define a string variable str. The string reverse command reverses the string, and the puts command prints the reversed string to the console. It's straightforward to understand.

A More Complex TCL Example

Now, let's look at a more convoluted TCL script that performs the same task but involves multiple steps and additional logic:

set str "Hello, World!"

set len [string length $str]

set reversed_str""

for {set i [expr $len - 1]} {$i >= 0} {incr i -1} {

}

}

puts $reversed_str

In this script, we first define the string variable str and calculate its length using the string length command. We initialize an empty string reversed_str. The for loop iterates over each character in the string from the end to the beginning, and the append command adds each character to the reversed_str. Finally, the puts command prints the reversed string to the console.

I think that we would all agree that, wherever possible, simplicity is preferred to needless complexity.

In the spirit of simplicity, I have created some videos showing some simple and useful commands in Innovus Implementation System Stylus Common UI.

Useful Commands to Get Design Information in Innovus Stylus Common UI Software (Video)

Useful General Purpose and Unix Commands used with Innovus Stylus Common UI Software (Video)

In the end, spaghetti has its place on your dinner table, not in your code. So, next time you're tempted to write that complex command, remember that a simple approach can save you time, effort, and a lot of headaches.

Related Resources

Innovus Block Implementation with Stylus Common UI Training Course

Tcl Scripting for EDA Training Course

Tcl Scripting for EDA + Intro to Tk Training Course

You might also be interested in the Learning Map, which guides you through recommended course flows as well as tool experience and knowledge-level training modules.

Find out how to get an account on the Cadence Learning and Support portal.

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Happy Coding!