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Training Insights – Dive into ATPG Flow with Cadence Modus DFT Software Solution

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The prominent components of the EDA flow, like synthesis, place and route, and signoff, sometimes receive more attention than ATPG (Automatic Test Pattern Generation) and testing, which are the red-headed stepchildren of the EDA process. Testing is a very essential step to ensure the accuracy and robustness of modern chips.

The Cadence Modus DFT Software Solution is a fully integrated suite of tools designed from the beginning to interact and work with each other. It is a complete tool suite supporting all four disciplines: Test synthesis, test analysis, test generation, and test diagnostics.

Modus DFT Software Solution provides:

  • Comprehensive manufacturing test offering for logic and embedded memory IP
  • Single pass logic synthesis, test insertion, and pattern generation, i.e., physically and power domain-aware
  • Reduced cost of defect detection with higher quality test patterns and accurate silicon defect diagnostics
  • Applicable to all design sizes from small mixed-signal to very large SoCs
  • Test coverage analysis and augmentation

Modus tightly integrates with Genus Synthesis Solution to help the user get up and start. Genus generates the downstream files to perform exhaustive testing, test point insertion, and reduced cost of defect detection.

Modus DFT Software Solution Components:

  • Modus scan offers DFT rule checking, test point insertion, and optimization
  • Modus scan tightly integrated into Genus
  • Modus ATPG
  • Modus diagnostics and trend analysis

One of the components of Modus DFT Software Solution is Modus ATPG, which creates the ATPG model, verifies the test structures and generates industry-standard test patterns to test the design and meet the coverage. Modus ATPG does this by:

  1. Reading the design netlist and the structural library files and combining them together to create a complete design image
  2. Specifying the test modes for testing the design
  3. Once the test modes are set, it runs the entire design checking for your circuit
  4. Then creates a fault database for ATPG processing
  5. Once the fault database is ready, Modus ATPG creates different types of tests and writes out the industry-standard vectors to test the design

Want to learn more about the ATPG process and broken scan chains debugging with Cadence Modus DFT Software Solution? We can also organize the “ATPG Flow with Modus DFT Software Solution” training for you as “Blended” or “Live” training. Please reach out to Cadence Training for further information.

Register for the Online Training with the following steps:

  • Log on to Cadence.com with your registered Cadence ID and password.
  • Select Learning from the menu > Online Courses.
  • Search for "ATPG Flow with Modus DFT Software Solution" using the search bar.
  • Select the course and click "Enroll" 

After completing the course, you can take the exam, and when you pass the exam, you will receive a badge that you can flaunt on social media.


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