In today's technology-driven world, there is an increasing need for semiconductor designs that are faster, more power-efficient, and highly robust. To meet this demand, semiconductor manufacturing companies constantly push the boundaries of technology scaling and innovation, even down to 2nm. Customers must analyze various effects to achieve the best PPA compared to current methods, such as applying global derates or margins, which can leave significant amounts of performance and power unused.
In response to these challenges, Cadence has continued to innovate and has created a suite of analysis capabilities that address these effects called the Cadence Tempus Design Robustness Analysis (DRA) Suite. This suite is equipped with advanced modeling algorithms that empower engineers to analyze, identify, and rectify critical design elements sensitive to variation using the Tempus ECO Option for block-level and Cadence Certus Closure Solution for subsystem/full-chip inthe Innovus Implementation System. By harnessing the advanced modeling capabilities of the suite, customers can enhance design-level robustness, improve power, performance, and area (PPA), and achieve up to a remarkable 10% boost in PPA compared to conventional, margin-based approaches.
The Tempus DRA Suite
The Tempus DRA Suite is a cutting-edge set of analysis capabilities that address design-level robustness against various forms of timing variation, including aging effects, voltage drop, and threshold voltage skew. This suite comprises five advanced analyses, each catering to specific aspects of robust semiconductor design:
1. Aging Robustness
The Tempus DRA Suite stands out in the industry with its exceptional aging robustness analysis capability, allowing it to enhance PPA by up to 10%. This analysis capability caters to a diverse range of sectors, including automotive, aerospace, consumer electronics, mobile devices, and hyperscale designs. The suite provides control over the aging characterization environment and requirements within the Cadence Liberate Library Characterization Flow. It offers a comprehensive view of aging contexts, with statistical graphs illustrating stress and recovery phases.
Aging robustness also incorporates aging-aware timing and constraints, delivering superior PPA with SPICE-level accuracy. Supported by TSMC TMI and other SPICE reliability models, it enables tracking arbitrary contexts during static timing analysis (STA), instance-specific aging, non-uniform aging, recovery modeling selection, and tunable settings for STA. This translates to faster design closure turnaround times by eliminating unnecessary delays attributed to aging effects.
2. Voltage Robustness
The voltage robustness analysis offers a groundbreaking signoff solution that seamlessly integrates with Tempus Power Integrity (PI) and Voltus IC Power Integrity solutions. This integration introduces next-generation IR (internal resistance) drop analysis and fixing technology. Voltage robustness automates the fixing process through the Tempus ECO Option and addresses IR drop issues by optimizing both victim and aggressor paths. Notably, it also identifies timing violations that conventional IR drop signoff methodologies may overlook, preventing costly silicon failures. By reducing the maximum IR drop design margin, it achieves optimal PPA.
3. Timing Robustness
The timing robustness analysis is the third feature of the Tempus DRA Suite. It is a powerful analysis capability for capturing timing correlations through statistical measurements of silicon performance. It adheres to Sigma reliability targets while significantly enhancing design PPA. Its user-friendly interface accelerates the ECO (engineering change order) cycle, offering a more straightforward alternative to traditional SPICE Monte Carlo analysis.
4. Silicon Prediction
The silicon prediction is the fourth analysis in the Tempus DRA Suite that focuses on the continuous tuning of silicon features. This provides rapid feedback on silicon device models, libraries, and target device models, allowing design engineers to make quicker adjustments to their designs. Silicon prediction is supported across various stages, including PBA (Physical Design, Build, and Analysis), GBA (Global Build and Analysis), Tempus Timing Solution, Tempus ECO Option, and Innovus Implementation System.
Design engineers leverage silicon prediction to establish model-to-hardware correlations, achieving desired silicon performance. Additionally, it delivers precise statistical modeling for identifying discrete parameters of silicon variations in pre-silicon signoff STA (static timing analysis) within the Tempus Timing and Liberate Characterization flow. This empowers teams to achieve true signoff and optimization, predict delays using silicon prediction, and improve PPA and timing yield predictions.
5. VT Skew Robustness
VT (voltage threshold) skew robustness is the fifth analysis capability of the Tempus DRA Suite. It addresses the inherent pessimism in current STA methodologies. With the Tempus DRA Suite, design engineers can analyze TT (temperature and voltage) corners with agility, performing rapid derating for each VT class to optimize delays toward slow and fast (SSG and FFG) corners. Designers can bundle libraries with VT classes and define slow and fast derating for each VT class. Tempus DRA Suite will run optimal permutations and identify worst-case slack based on the launch and capture path compositions of VT classes.
The Tempus DRA Suite introduces a comprehensive suite of advanced analyses that promise to enhance design-level robustness and deliver exceptional improvements in PPA compared to traditional methodologies. With its focus on aging robustness, voltage robustness, timing robustness, silicon prediction, and VT skew robustness, this suite empowers design teams to create semiconductor solutions that are more efficient, reliable, and competitive in today's fast-paced technological environment. It is a pivotal step toward the next generation of semiconductor design.
Tempus DRA Suite is part of the broader digital and signoff flow and supports Cadence Intelligent System Design strategy, enabling system-on-chip (SoC) design excellence. Learn more about the advanced analysis features of the Tempus Timing Solution.