With advanced-process nodes, a standard cell's physical delay, net delay, and congestion lead to a higher netlist requirement.
Do you want to tackle congestion and achieve a better PPA for your design?
If so, it's time to gear up with Cadence Genus iSpatial Synthesis flow with Cadence Training and Sr. Principal Education Application Engineer Neha Joshi in the recorded session of the Training Webinar held in May 2023.
Genus iSpatial bridges synthesis and implementation with integrated core engines and unified physical optimization. It provides great power, performance, and area (PPA) results in full flow. iSpatial enables front-end designers to make better design decisions faster by providing physical feedback about expected Place and Route (P&R) effects. This delivers better PPA results in complex SoC designs while maintaining quality and design schedules.
In this webinar, we'll dive into the following:
- What is the Genus iSpatial Synthesis flow?
- How do Cadence's Genus Synthesis Solution and Innovus Implementation System interface?
- What are the features of the Genus layout graphical user interface (GUI)?
- How to handle incomplete/missing collateral using the predict floorplan flow?
Want to dive deep into the Genus iSpatial Synthesis Flow?
- You can explore this exciting flow with hands-on labs in both the Genus Synthesis Solution with Stylus Common UI and Advanced Synthesis with Genus Stylus Common UI
- Please note that there is also a Digital Badge available for both classes.
- You can become Cadence Certified once you complete the course (s) and share your knowledge and certifications on social media channels.
Related Training bytes and RAKs that might be interesting:
- How to Enable Early Clock Flow (ECF) in Genus iSpatial Synthesis? (Video)
- iSpatial Basic Debugging (Video)
- iSpatial: Next-Generation Common Physical Optimization Flow in Genus Synthesis Solution (Video)
- Genus iSpatial Flow - Next-Generation Common Physical Optimization flow (RAK)
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Learn more about the Genus Synthesis Solution, delivering the best possible productivity during RTL design and the highest quality of results (QoR) in final implementation.