Optimizing power can be a very convoluted and crucial process. To make design chips meet throughput goals and optimal power consumption, you need to plan right from the beginning! Power is HOT and touches everything and everybody!
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Low-power synthesis is one of the important stages in the full IC flow. Using various techniques, you synthesize the design from behavioral description to gates while optimizing for dynamic and leakage power. Do you want to use multiple supply voltage (MSV) design, power shutoff (PSO) synthesis, dynamic voltage frequency scaling (DVFS), or other techniques to optimize your power results?
But stuck as you are new to the low-power world, do the various power terminologies look like a complicated maze for you?
- Power domains
- Power intent
- Power modes
- Level shifter
- Isolation logic
- State retention power gating
- Gate-level dynamic power optimization
- Clock gating
- Multiple threshold voltage
- Power shutoff
- Dynamic voltage frequency scaling
- Glitch
The list goes on…
Wondering how to enhance your knowledge of these concepts to ensure proper planning for low-power optimization? Gear up! You don't need too many resources to elevate your proficiency.
We believe disseminating the knowledge amplifies its power. We want you to leverage our vast resources to develop expertise and knowledge of various chip design concepts and flows. The magic lies in your pocket! Unlock your mobile and start relaxing with YouTube videos!
Er…don't get confused! The Cadence YouTube channel hosts a Customer Education Training Bytes channel. This provides a video repository of short conceptual videos on YouTube. The learning is just a click away! Click the links below to explore the basic low-power terminologies and more!
What Is State Retention Power Gating
How to do Gate Level Dynamic Power Optimization
What is Clock Gating and How to Reduce Clock Power
Understanding Multiple Threshold Voltage Optimization
What Are Multiple Supply Voltage and Power Shutoff Methodologies?
What Is Dynamic Voltage Frequency Scaling
As a next step, you can further leverage the vast database of videos and detailed training on Cadence Application Support and Knowledge Portal (Cadence login required).
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Related Courses
- Fundamentals of IEEE 1801 Low-Power Specification Format
- Genus Low-Power Synthesis Flow with IEEE 1801
- Genus Physical Synthesis Flow
- Genus Synthesis Solution with Stylus Common UI
- Joules Power Calculator
- Low-Power Synthesis Flow with Genus Stylus Common UI
- Test Synthesis with Genus Stylus Common UI
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