With highly advanced technology, the real designs are getting complex, making the design optimization process complicated and comprising the design results. The sequential cells play a vital role in the chip's optimization and functioning.
Constant, merged, and unused flops, among other factors, impact the chip design's power, performance, and area (PPA) during the synthesis stage. Is there any way to handle the flops optimization for the best PPA results?
The solution lies with the Cadence Genus Synthesis Solution. The ultimate goal of the Genus Synthesis Solution is very simple: deliver the best possible productivity and Power, Performance, and Area (PPA) during register-transfer-level (RTL) logic synthesis of the chip.
How do you manage the flop optimization?
- Unused registers on selected modules
- Disabling sequential merging
- Optimizing constants on specific flops
- Preventing register deletion
- Preventing Selective registers during elaboration
- Preventing merging of specific flops
Do you want to know how Genus Synthesis Solution manages all these? Explore the videos that cover how to control or enable/disable the optimization of registers or sequential elements in Genus. You can refer to the videos on the ASK Portal (Cadence login required).
Video Links
Removing Unused Registers on Selected Modules in Genus Synthesis Solution (Video)
Preventing Register Deletion in Genus Synthesis Solution (Video)
Disabling Sequential Merging in Genus Synthesis Solution (Video)
Preventing Merging of Specific Flops in Genus Synthesis Solution (Video)
Preserving Selective Registers During Elaboration in Genus Synthesis Solution (Video)
Optimizing Constants On Specific Flops in Genus Synthesis Solution (Video)
Related Resources
Video Links: Enhance your knowledge of Genus and Joules with short videos
Want to Learn More?
Explore the one-stop solution product pages on the Application Support and Knowledge Portal (Cadence login required).
Related Courses
- Genus Synthesis Solution with Stylus Common UI
- Advanced Synthesis with Genus Stylus Common UI
- Low-Power Synthesis with Genus Stylus Common UI
- Genus Low-Power Synthesis Flow with IEEE1801
- Test Synthesis with Genus Stylus Common UI
- Joules Power Calculator
- Fundamentals of IEEE1801 Low-Power Specification Format
Want to Enroll in this Course?
We've organized this training for you as "blended" or "Live" training. Please reach out to Cadence Training for further information.
If you want to ensure you are always the first to know about anything new in training, you can use the SUBSCRIBE button on the landing page to sign up for our regular training newsletters.
What's Next?
Grab your Digital Badge after finishing the training and flaunt what expertise you have built up. 😊
Please don't forget to obtain your Digital Badge after completing the training.
Related Blogs
It's the Digital Era; Why Not Showcase Your Brand Through a Digital Badge!