In this training webinar, we explore the concepts of RTL design, design verification, and coverage analysis while unveiling the exciting world of front-end design flow. We will guide you through the essential steps in creating integrated circuits, the building blocks of modern electronics.
We’ll break down the process into manageable stages, from defining the chip’s functionality to its physical realization. We’ll investigate the front-end part of the RTL-to-GDSII flow—from specification to functional verification and design coverage—and explore:
- Key concepts of specifying chip behavior and performance
- How to translate ideas into a digital blueprint and transform that into a design
- How to ensure your design is free of errors
This webinar provides practical knowledge, making it your gateway to understanding the magic behind RTL-to-GDSII front-end design flow.
When Is the Webinar?
Date and Time
Wednesday, September 18, 2024
07:00 PDT San Jose / 10:00 EDT New York / 15:00 BST London / 16:00 CEST Munich / 17:00 IDT Jerusalem / 19:30 IST Bangalore / 22:00 CST Beijing
To register for this webinar, sign in with your Cadence Support account (email ID and password) to log in to the Learning and Support System.
Then select Enroll to register for the session. Once registered, you’ll receive a confirmation email containing all login details.
If you don’t have a Cadence Support account, go to Cadence User Registration and complete the requested information. Or visit Registration Help.
For inquiries or issues with registration, reach out to eur_training@cadence.com.
For inquiries or issues with registration, reach out to eur_training@cadence.com.
To view our complete training offerings, visit the Cadence Training website.
Want to share this and other great Cadence learning opportunities with someone else? Tell them to subscribe.
Want to Learn More?
This link gives you more information about the related training course and a link to enroll:
Cadence RTL-to-GDSII Flow Training
The course includes slides with audio and downloadable laboratory exercises designed to emphasize the topics covered in the lecture. There is also a Digital Badge available for the training.
The online class is free for all Cadence customers with a Cadence Learning and Support Portal account. For instructor-led training sessions "Live" or "Blended" please contact Cadence Training.
Also, take this opportunity to register for the free Online Trainings related to this webinar topic.
Verilog Language and Application
Related Training Bytes
How to Run the Synthesis Without DFT?
How to Run the Synthesis Flow with DFT? (Video)
Related Blogs
Did You Miss the RTL-to-GDSII Webinar? No Worries, the Recording Is Available!
Training Insights – Why Is RTL Translated into Gate-Level Netlist?
Training Bytes: They May Be Shorter, But the Impact Is Stronger!
Cadence Support - A Round-the-Clock Problem Solver, Webinar Recording Available!