Traditionally, you would do power, performance, area, and congestion (PPAC) analysis for a design as you move forward with different stages in the flow.
But with highly advanced technology, the real designs are getting complex and interdependent, complicating the analysis at each stage!! Hence, attaining PPAC goals can be very convoluted and crucial as the clock keeps ticking for the tapeout time. What is the challenge here?
As an RTL designer, the challenge is quickly debugging the source code at a stage where critical timing and congestion problems must be resolved.
What's needed here is an early insight into power, performance, area, and congestion!
The ability to perform accurate RTL analyses and intelligent debugging prior to handing the design to the synthesis and physical design teams is necessary for design teams to meet competitive schedules and get differentiated products to market on time. How do we cater to this need?
The key is to empower the front-end designers with technology that enables fully optimized RTL for implementation handoff and provides RTL designers with capabilities to assist in the implementation convergence process. An important factor for front-end designers' success is having their analysis results delivered quickly without compromising accuracy and vice-versa.
The question is how?
The solution lies with Cadence Joules RTL Design Studio, an expert system that triages possible causes of violations and additional insights that empower designers to understand how to address issues in their RTL, leading to smarter and more efficient chip design.
Joules RTL Design Studio can customize the runtime versus accuracy tradeoff depending on the end goal of the design. Joules RTL Design Studio is a user-centered solution that considers the gamut of requirements of front-end teams.
Now comes the plan for the new year to start with the best PPAC results!
How do you ramp up on this technology and become an expert in efficiently optimizing the results using Joules Studio?
Don't worry; we are here to sail you through this journey!!
The solution is in the form of videos that explore the Joules RTL Design Studio GUI features and how you can use various features to analyze the PPAC results.
You can refer to the videos on Cadence Online Support(Cadence login required).
Video Links
Exploring Joules RTL Design Studio GUI (Video)
Exploring Checkers Widget in Joules RTL Design Studio (Video)
Exploring analyze_bottleneck Command of Joules RTL Design Studio (Video)
Exploring Power Intent Schematic Viewer in Joules RTL Design Studio (Video)
Exploring Global Timing Debugger in Joules RTL Design Studio (Video)
Exploring Design Browser of Joules RTL Design Studio GUI (Video)
And the list goes on.
Want to learn more?: Explore the one-stop solutionJoules RTL Design Studio Product Page on Cadence Online Support(Cadence login required).
Related Resources
Related Training Bytes
Understanding Analyze Timing By Hierarchy In Joules RTL Design Studio (Video)
Understanding Analyze Congestion By Hierarchy In Joules RTL Design Studio (Video)
Exploring Analyze_bottleneck Command Of Joules RTL Design Studio (Video)
Understanding Analyze Timing By Category In Joules RTL Design Studio (Video)
Exploring RTL Diff Utility Of Joules RTL Design Studio (Video)
Understanding The Analyze_path Command Of Joules RTL Design Studio (Video)
Understanding The Analyze_timing Command Of Joules RTL Design Studio (Video)
Exploring Power Intent Schematic Viewer In Joules RTL Design Studio (Video)
Exploring Checkers Widget In Joules RTL Design Studio (Video)
Understanding The Analyze_depth Command Of Joules RTL Design Studio (Video)
Click here to view more.
Related Courses
Want to enroll in this course? We've organized this training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information.
Please don´t forget to obtain your Digital Badge after completing the training.
