Semiconductor chips must be designed faster, smaller, and smarter—with less manual work, more automation, and faster production.
The Training Webinar “Flow Wrapping: The Cadence Cerebrus Intelligent Chip Explorer Must Have” was recently hosted with me, Krishna Atreya, Principal Education Application Engineer.
The webinar recording is now available as a Training Byte, 24/7, for everyone with a Cadence Support account*.
Watch:Flow Wrapping: The Cadence Cerebrus Intelligent Chip Explorer Must Have
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Block engineers specify the design goals, and Cadence Cerebrus intelligently optimizes the Cadence digital full flow to meet power, performance, and area (PPA) goals in a completely automated way—letting engineers concurrently optimize multiple block flows.
Check out the Cadence Cerebrus Intelligent Chip Explorer course to learn more.
There is also a Digital Badge available for the training.
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