Five-Minute Tutorial: Set Flip-Chip Bumps as Voltage Sources in EPS/EDI Rail Analysis

When running power and rail analysis for a flip chip, we used to have to spend some time creating the voltage sources. It wasn't too terrible; usually we would output the bumps into a Cadence Encounter Digital Implementation (EDI) .io file, then use a perl script to filter out the pwr/gnd bumps and create the voltage source file format. The script would need a bit of editing from project to project, but nothing too complicated. We ended up with a voltage source file, with one point-source per bump. However, it is much easier these days to create voltage sources for a flip chip to be used in the Cadence Encounter Power System (EPS) Rail Analysis (run either from EPS directly, or through EDI.) It is also more accurate, since the bumps get modeled with several points in a resistor network. (This will avoid false EM violations.)

The LEF file of your flip chip bump will be used as a reference. Bumps are usually octagonal, although sometimes are represented as squares. Here is an example bump LEF, which I will use to illustrate the process. (Note that a polygon shape is used to create an octagonal bump, but the corresponding coordinates that would have been used for a square are commented out.)

VERSION 5.6 ;
BUSBITCHARS "[]" ;
DIVIDERCHAR "/" ;
UNITS
  DATABASE MICRONS 1000 ;
END UNITS

MACRO BUMP
 CLASS COVER BUMP ;
 FOREIGN BUMP -49.45 -49.45 ;
 ORIGIN 49.45 49.45 ;
 SIZE 98.9 BY 98.9 ;
 PIN PAD
    DIRECTION INOUT ;
    USE SIGNAL ;
    PORT
      LAYER AP ;
        #RECT -49.45 -49.45 49.45 49.45 ;
        POLYGON -20.49 -49.45 20.49 -49.45 49.45 -20.49 49.45 20.49 20.49 49.45 -20.49 49.45 -49.45 20.49 -49.45 -20.49 ;
    END
  END PAD
END BUMP

END LIBRARY

First, create a file called bump.padfile. This file contains one line, the MACRO name of the bump from the LEF. It should look like this:

BUMP

Next, create a file called bump.srcfile. It should look like this:

CELL BUMP
  NET PAD
  PORT {
    AP -49.45 -49.45 49.45 49.45
  }

Make sure the CELL and NET names match your bump LEF. The NET name is the PIN name from the LEF. The port layer name (AP here) is the same layer from the LEF. Remember the commented-out square coordinates that I mentioned in the LEF example above? Here is where that's useful: the coordinates of the PORT shape should be a square that encloses the octagonal bump.

Now, create the bump powergrid view. Here is a sample script, called create_bump_pwrgrid.ss0p81v.tcl:

read_lib -lef tech.lef \
   BUMP.lef

set_power_library_mode \
    -accuracy fast \
    -celltype allcells \
    -extraction_tech_file cworst.qrcTechFile \
    -lef_layermap lef_layer.map \
    -generic_power_names {VDD 0.81} \
    -generic_ground_names {VSS} \
    -input_type pr_lef

characterize_power_library \
    -celllist_file bump.list \
    -padvsrcfile bump.srcfile \
    -libgen_command_file libgen.inc \
    -output_directory fast_bump.ss_0p81v

A few notes about the files referenced in this script:

• The bump.list file just contains the bump name and is actually the same as the bump.padfile.
• For an example of the lef_layer.map file, see my last blog, Five-Minute Tutorial: Create Encounter Power System (EPS) Power-Grid Views For Standard Cells.
• The libgen.inc file looks like this (again, the cell and net name should match the bump LEF):
  cell_common_supply_names cell BUMP nets {PAD}

Finally, when running rail analysis, use the bump.padfile in your set_power_pads command. The same padfile can be used for any rail:

set_power_pads \
  -net VDD \
  -format padcell \
  -file bump.padfile

set_power_pads \
  -net VSS \
  -format padcell \
  -file bump.padfile

All bumps will then be recognized as voltage sources, with multiple points inside the bump shape. I hope this has helped simplify your rail analysis flow!

- Kari Summers