At advanced nodes, there’s always a deep conflict between power, performance, and area (PPA) and design turnaround time (TAT). You already know Innovus Implementation System very smartly delivers PPA advantage and accelerates digital design TAT through various features, including its full-flow massively parallel architecture. Innovus 18.10 release takes all these benefits even further. In this blog, I will start with sharing some key highlights of 18.1 release and eventually share pointers of several technical content to learn and leverage the new release capabilities.
Some of the key highlights are listed below:
This easily translates to some key benefits for our customers:
TAT:
- Native speedup for Optimization engines
- Up to 3x speedup for core CTS
- More multi-thread parallelization
PPA:
- SOCV aware placement in addition to optimization
- Global Sizing for efficient timing closure
- Full flow improved data and clock power, including timing and power-driven routing
Usability:
- Enhanced clock H-Tree capabilities
- New Graphical metrics reporting
- 3D layout GUI, Stylus Common UI Production, Design data sanity checking
Advanced node features and support:
Digital and Sign-off 18.1 release page captures variety of content available for several products viz. Genus, Modus, Conformal, Innovus, Tempus, Voltus etc. that you could leverage to complete your full digital design flow. This not only has various update trainings explaining new features, but also posses multiple key learning content like RAKs, Videos, etc., pertaining to 18.1 release.
Click here to access 18.1 release Page. If click to the link does not work, use direct URL: https://support.cadence.com/dsg181 on your browser window to access release page.
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~ Mukesh Jaiswal